Visible to Intel only — GUID: xnp1494232240383
Ixiasoft
Visible to Intel only — GUID: xnp1494232240383
Ixiasoft
5.3. Commands and Responses
The first word of the command and response packets is a header that provides basic information about the command or response.
Block Diagram
The following figure illustrates the role of the Mailbox Client Intel® FPGA IP in a Agilex™ 5 design. The Mailbox Client Intel® FPGA IP enables communication with the SDM to access quad SPI flash memory and system status.
The following table describes the fields of the header command.
Header | Bit | Description |
---|---|---|
CLIENT | [31:28] | The client ID. The response header returns the client ID specified in the command header. |
ID | [27:24] | The command ID. The response header returns the ID specified in the command header. Refer to Operation Commands for command descriptions. |
0 | [23] | Reserved. |
LENGTH | [22:12] | Number of words of arguments following the header. The IP responds with an error if a wrong number of words of arguments is entered for a given command. If there is a mismatch between the command length specified in the command header and the number of words sent. The IP raises bit 3 of the Interrupt Status Register (COMMAND_INVALID) and the Mailbox Client Intel® FPGA IP must be reset. |
Reserved | [11] | Reserved. Must be set to 0. |
Command Code/Error Code | [10:0] | Command Code specifies the command. The Error Code indicates whether the command succeeded or failed. In the command header, these bits represent command code. In the response header, these bits represent error code. If the command succeeds, the Error Code is 0. If the command fails, refer to the error codes defined in the Error Code Responses. |