Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs

ID 813773
Date 4/01/2024
Public

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3.1.7.1. Functional Description

You can use the Parallel Flash Loader II Intel® FPGA IP with an external host, such as the MAX® II, MAX® V, or MAX® 10 devices to complete the following tasks:

  • Program configuration data into a flash memory device using JTAG interface.
  • Configure the Agilex™ 5 device with the Avalon® -ST configuration scheme from the flash memory device.
Note: Use the Parallel Flash Loader II Intel® FPGA IP with the Avalon® -ST configuration scheme in Agilex™ 5 devices, not the earlier Parallel Flash Loader Intel® FPGA IP.
Note: The current implementation does not support programming two QSPI devices with two separate PFL images in a single programming cycle. To program multiple QSPI devices, you must program each QSPI flash device with a single PFL image separately.
Note: The Parallel Flash Loader II Intel® FPGA IP does not support HPS cold reset.