1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 813667
Date 10/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY IP for Agilex™ 3 and Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY IP 5. Interface Signals 6. Configuration Registers 7. Troubleshooting and Debugging Diagnostics 8. 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY IP for Agilex™ 3 and Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to IP 2.2. Installing and Licensing IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing IPs x
2.2.1. IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the GTS System PLL Clocks IP
3. Functional Description x
3.1. Architecture 3.2. Dynamic Reconfiguration Flow 3.3. Clocking and Reset Sequence 3.4. Timing Constraints 3.5. Operation Speed Switching 3.6. USXGMII 3.7. Fmax Requirement
3.1. Architecture x
3.1.1. 1G, 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) 3.1.2. 10M/100M/1G/2.5G/5G/10G (USXGMII) (NBASE) 3.1.3. 1G/2.5G/10G MGBASE PCS only
3.2. Dynamic Reconfiguration Flow x
3.2.1. RTL Generation using Dynamic Reconfiguration IP
3.2.1. RTL Generation using Dynamic Reconfiguration IP x
3.2.1.1. Step 1: Generating the 1G/2.5G/5G/10G Multirate Ethernet PHY IP 3.2.1.2. Step 2: QSF settings and Dynamic Reconfiguration (DR) profile assignments 3.2.1.3. Step 3: RTL Generation using Quartus® Prime Pro Edition Tool 3.2.1.4. Step 4: Instantiate the IP top file with the GTS Dynamic Reconfiguration Controller IP
3.3. Clocking and Reset Sequence x
3.3.1. Clocking 3.3.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration Controller Interface Signals
5.6. GMII Signals x
5.6.1. 1G/2.5G/10G MGBASE PCS Only PMA Interface
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
7. Troubleshooting and Debugging Diagnostics x
7.1. Troubleshooting Checklist 7.2. Enabling Diagnostic Loopback Modes 7.3. Recommended Reset Handling 7.4. Troubleshooting Using the Signal Tap Analyzer
7.2. Enabling Diagnostic Loopback Modes x
7.2.1. Internal Serial Loopback 7.2.2. External Loopback
7.4. Troubleshooting Using the Signal Tap Analyzer x
7.4.1. Signals for Signal Tap
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY IP for Agilex™ 3 and Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY IP
5. Interface Signals
6. Configuration Registers
7. Troubleshooting and Debugging Diagnostics
8. 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

7.1. Troubleshooting Checklist

Table 32.  Troubleshooting Checklist
Issue Troubleshooting Checklist
The ethernet link fails to come up

Follow these troubleshooting steps to resolve the issue:

  • Review the IP configuration in the parameter editor to ensure it matches the requirements.
  • Perform external loopback test.
  • Perform serial internal loopback test.
  • The following status signals should go high once the RX reset is successfully completed:
    • MGBASE variant: rx_ready, tx_ready, led_link, and o_rx_block_lock.
    • NBASE variant: o_rx_pcs_ready and o_tx_lanes_stable.
  • Confirm that all required reset inputs are properly driven as described in the Reset Sequence.
  • Confirm that all specified clock inputs are correct as described in the Clocking.
Ethernet link is unstable

Follow these troubleshooting steps to resolve the issue:

  • Review the IP configuration in the parameter editor to ensure it matches the requirements.
  • Perform external loopback test.
  • Perform serial internal loopback test.
  • Check that the PMA analog settings in the parameter editor are configured according to the specified link profile.
  • Verify that tx_clkout and rx_clkout are as expected for MGBASE and NBASE design variants.
Ethernet link high-bit error rate

Follow these troubleshooting steps to resolve the issue:

  • Review the IP configuration in the parameter editor to ensure it matches the requirements.
  • Perform external loopback test.
  • Perform serial internal loopback test.
  • Check that the PMA analog settings in the parameter editor are configured according to the specified link profile.
Missing ethernet packets at the receiver side.

Follow these troubleshooting steps to resolve the issue:

  • Review the IP configuration in the parameter editor to ensure it matches the requirements.
  • Verify that the reference clock value provided in hardware matches the value specified in the 1G/2.5G/5G/10G Multirate Ethernet PHY IP. For clocking requirements specific to variants, refer to Clocking.
  • Perform serial internal loopback test.
  • Check that the PMA analog settings in the parameter editor are configured according to the specified link profile.
The IP is not responding to the data flow Follow these troubleshooting steps to resolve the issue:
  • Review the IP configuration in the parameter editor to ensure it matches the requirements.
  • Monitor the Avalon® memory-mapped interface and Avalon® streaming interface control and status signals.
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