1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813667
Date 8/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY IP for Agilex™ 3 and Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY IP 5. Interface Signals 6. Configuration Registers 7. Debug Checklist 8. 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY IP for Agilex™ 3 and Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to IP 2.2. Installing and Licensing IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing IPs x
2.2.1. Altera FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the GTS System PLL Clocks IP
3. Functional Description x
3.1. Architecture 3.2. Dynamic Reconfiguration Flow 3.3. Clocking and Reset Sequence 3.4. Timing Constraints 3.5. Operation Speed Switching 3.6. USXGMII 3.7. Fmax Requirement
3.1. Architecture x
3.1.1. 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) 3.1.2. 10M/100M/1G/2.5G/5G/10G (USXGMII) 3.1.3. 1G/2.5G/10G MGBASE PCS only
3.2. Dynamic Reconfiguration Flow x
3.2.1. RTL Generation using Dynamic Reconfiguration IP
3.2.1. RTL Generation using Dynamic Reconfiguration IP x
3.2.1.1. Step 1: Generating the 1G/2.5G/5G/10G Multirate Ethernet PHY IP 3.2.1.2. Step 2: QSF settings and Dynamic Reconfiguration (DR) profile assignments 3.2.1.3. Step 3: RTL Generation using Quartus® Prime Pro Edition Tool 3.2.1.4. Step 4: Instantiate the IP top file with the GTS Dynamic Reconfiguration Controller IP
3.3. Clocking and Reset Sequence x
3.3.1. Clocking 3.3.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration Controller Interface Signals
5.6. GMII Signals x
5.6.1. 1G/2.5G/10G MGBASE PCS Only PMA Interface
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
7. Debug Checklist x
7.1. Pre-Debugging Process 7.2. Clock Frequency 7.3. Recommended Reset Handling 7.4. Signals for Signal Tap
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY IP for Agilex™ 3 and Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY IP
5. Interface Signals
6. Configuration Registers
7. Debug Checklist
8. 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

3.3.1. Clocking

Clocking requirements:
  • tx_pll_refclk signal is the TX path reference clock for the PMA PLL. It is used to generate the serial clock and the parallel data clocks. Altera recommends that you use 156.25 MHz frequency for the tx_pll_refclk signal. Altera also recommends using the same clock for rx_cdr_refclk.
  • For 8-bit GMII (MGBASE):
    • The GMII 8-bit adapter generates the gmii8b_tx_clkout clock signal. For 10M, the clock frequency is 2.5 MHz. For 100M (MII, 4-bit interface), the clock frequency is 25 MHz. For 1G and 2.5G (8-bit interface), the clock frequency is 125 MHz and 312.5 MHz respectively.
    • The Hard Processor System (HPS) Ethernet Media Access Controller (MAC) drives the gmii8b_tx_clkin signal at the same frequency with the gmii8b_tx_clkout signal.
    • The refclk frequency for MRPHY_PLL is 62.5 MHz for 1G and 156.25 MHz for 2.5G.
  • For 16-bit GMII (MGBASE), the transmit is clocked by tx_clkout. The PHY drives this clock to the MAC. The primary clock frequencies for 1G and 2.5G are 62.5 MHz and 156.25 MHz, respectively. For 10M and 100M, the primary clock frequency is 62.5 MHz with clock enable.
  • xgmii_tx_coreclkin and xgmii_rx_coreclkin are available in MGBASE (10G) only.
  • For the USXGMII mode, the MAC drives the xgmii_tx_coreclkin to the PHY with a single clock frequency of 312.5 MHz.
Note: When instantiating the 1G/2.5G/5G/10G Multirate Ethernet PHY IP in the design, you must follow the shared clocking consideration specified in the Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank section of the GTS Transceiver PHY User Guide.
Table 11.  Clocking Specifications
Clock Signals 10M (MII) 100M (MII) 1G (GMII) 2.5G
MGBASE (8-bit)

gmii8b_tx_clkin/gmii8b_tx_clkout

gmii8b_rx_clkin/gmii8b_rx_clkout

 2.5 MHz

(4-bit interface)

 25 MHz

(4-bit interface)

 125 MHz

(8-bit interface)

312.5 MHz

(8-bit interface)
Figure 10. 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) Clocking
Figure 11. 10M/100M/1G/2.5G/5G/10G (NBASE) Clocking
Figure 12. 1G/2.5G/10G MGBASE PCS Only Clocking
Related Information
Level Two Title