1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 813667
Date 10/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY IP for Agilex™ 3 and Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY IP 5. Interface Signals 6. Configuration Registers 7. Troubleshooting and Debugging Diagnostics 8. 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY IP for Agilex™ 3 and Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to IP 2.2. Installing and Licensing IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing IPs x
2.2.1. IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the GTS System PLL Clocks IP
3. Functional Description x
3.1. Architecture 3.2. Dynamic Reconfiguration Flow 3.3. Clocking and Reset Sequence 3.4. Timing Constraints 3.5. Operation Speed Switching 3.6. USXGMII 3.7. Fmax Requirement
3.1. Architecture x
3.1.1. 1G, 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) 3.1.2. 10M/100M/1G/2.5G/5G/10G (USXGMII) (NBASE) 3.1.3. 1G/2.5G/10G MGBASE PCS only
3.2. Dynamic Reconfiguration Flow x
3.2.1. RTL Generation using Dynamic Reconfiguration IP
3.2.1. RTL Generation using Dynamic Reconfiguration IP x
3.2.1.1. Step 1: Generating the 1G/2.5G/5G/10G Multirate Ethernet PHY IP 3.2.1.2. Step 2: QSF settings and Dynamic Reconfiguration (DR) profile assignments 3.2.1.3. Step 3: RTL Generation using Quartus® Prime Pro Edition Tool 3.2.1.4. Step 4: Instantiate the IP top file with the GTS Dynamic Reconfiguration Controller IP
3.3. Clocking and Reset Sequence x
3.3.1. Clocking 3.3.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration Controller Interface Signals
5.6. GMII Signals x
5.6.1. 1G/2.5G/10G MGBASE PCS Only PMA Interface
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
7. Troubleshooting and Debugging Diagnostics x
7.1. Troubleshooting Checklist 7.2. Enabling Diagnostic Loopback Modes 7.3. Recommended Reset Handling 7.4. Troubleshooting Using the Signal Tap Analyzer
7.2. Enabling Diagnostic Loopback Modes x
7.2.1. Internal Serial Loopback 7.2.2. External Loopback
7.4. Troubleshooting Using the Signal Tap Analyzer x
7.4.1. Signals for Signal Tap
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY IP for Agilex™ 3 and Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY IP
5. Interface Signals
6. Configuration Registers
7. Troubleshooting and Debugging Diagnostics
8. 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

5.5. XGMII Signals

Table 21.  XGMII Signals
Signal Name Direction Width Description PHY Configurations
XGMII Transmit
xgmii_tx_control Input 4, 8 TX control from the MAC. The xgmii_tx_control bit corresponds to the xgmii_tx_data bits. For example, xgmii_tx_control[0] corresponds to xgmii_tx_data[7:0] and xgmii_tx_control[1] corresponds to xgmii_tx_data[15:8].
The width is:
  • 8 bits for 1G/2.5G/10G (MGBASE) configurations.
  • 4 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.
  • 1G/2.5G/10G (MGBASE)
  • 10M/100M/1G/2.5G/10G (MGBASE)
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
  • 1G/2.5G/10G MGBASE PCS only
xgmii_tx_data Input 32, 64 TX data from the MAC. The MAC sends the data in the following order: bits [7:0], bits [15:8], bit [23:16], and so on.
The width is:
  • 64 bits for 1G/2.5G/10G (MGBASE) configurations.
  • 32 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.
xgmii_tx_valid Output 1 Indicates valid data on xgmii_tx_control and xgmii_tx_data from the MAC.
Your logic/MAC must toggle the valid data as shown below:
Speed Toggle Rate
10M Asserted once every 1000 clock cycles
100M Asserted once every 100 clock cycles
1G Asserted once every 10 clock cycles
2.5G Asserted once every 4 clock cycles
5G Asserted once every 2 clock cycles
10G Asserted on every clock cycle
NBASE variant:

10M/100M/1G/2.5G/5G/10G (USXGMII)
xgmii_tx_latency Output 16/24 (USXGMII) TX XGMII datapath latency for IEEE 1588v2, measured from XGMII user interface to PCS-PMA interface.
  • [15:10] Number of clock cycle
  • [9:0] Fractional number of clock cycle
Note: For USXGMII configuration, the latency value may be unstable for the first three transmitted packets times (at least 64 bytes). You should not use the latency value within this period.
10M/100M/1G/2.5G/5G/10G (USXGMII) with IEEE I588v2
XGMII Receive
xgmii_rx_control Output 4, 8 RX control to the MAC. The xgmii_rx_control bit corresponds to the xgmii_rx_data bits. For example, xgmii_rx_control[0] corresponds to xgmii_rx_data[7:0] and xgmii_rx_control[1] corresponds to xgmii_rx_data[15:8]

The width is:

  • 8 bits for 1G/2.5G/10G (MGBASE) configurations.
  • 4 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.
.
  • 1G/2.5G/10G (MGBASE)
  • 10M/100M/1G/2.5G/10G (MGBASE)
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
  • 1G/2.5G/10G MGBASE PCS only
xgmii_rx_data Output 32, 64 RX data to the MAC. The PHY sends the data in the following order: bits [7:0], bits [15:8], bit [23:16], and so on.

The width is:

  • 64 bits for 1G/2.5G/10G (MGBASE) configurations.
  • 32 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.
xgmii_rx_valid Output 1 Indicates valid data on xgmii_rx_control and xgmii_rx_data from the MAC.
The toggle rate from the PHY is shown in the table below.
Speed Toggle Rate
10M Asserted once every 1000 clock cycles
100M Asserted once every 100 clock cycles
1G Asserted once every 10 clock cycles
2.5G Asserted once every 4 clock cycles
5G Asserted once every 2 clock cycles
10G Asserted on every clock cycle
Note: The toggle rate may vary when the start of a packet is received or when rate match occurs inside the PHY. You should not expect the valid data pattern to be fixed.
NBASE variant:

10M/100M/1G/2.5G/5G/10G (USXGMII)
xgmii_rx_latency Output 16/24 (USXGMII) RX XGMII datapath latency for IEEE 1588v2, measured from PCS-PMA interface to XGMII user interface.
  • [15:10] Number of clock cycle
  • [9:0] Fractional number of clock cycle
Note: For USXGMII configuration, the latency value may be unstable for the first three transmitted packets times (at least 64 bytes). You should not use the latency value within this period.
10M/100M/1G/2.5G/5G/10G (USXGMII) with IEEE I588v2
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