1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 813667
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 3 and Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP 5. Interface Signals 6. Configuration Registers 7. Debug Checklist 8. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 3 and Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the GTS System PLL Clocks IP
3. Functional Description x
3.1. Architecture 3.2. Dynamic Reconfiguration Flow 3.3. Clocking and Reset Sequence 3.4. Timing Constraints 3.5. Operation Speed Switching 3.6. USXGMII 3.7. Fmax Requirement
3.1. Architecture x
3.1.1. 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) 3.1.2. 10M/100M/1G/2.5G/5G/10G (USXGMII) 3.1.3. 1G/2.5G/10G MGBASE PCS only
3.2. Dynamic Reconfiguration Flow x
3.2.1. RTL Generation using Dynamic Reconfiguration IP
3.2.1. RTL Generation using Dynamic Reconfiguration IP x
3.2.1.1. Step 1: Generating the 1G/2.5G/5G/10G Multirate Ethernet PHY IP 3.2.1.2. Step 2: QSF settings and Dynamic Reconfiguration (DR) profile assignments 3.2.1.3. Step 3: RTL Generation using Quartus® Prime Pro Edition Tool 3.2.1.4. Step 4: Instantiate the IP top file with the GTS Dynamic Reconfiguration Controller IP
3.3. Clocking and Reset Sequence x
3.3.1. Clocking 3.3.2. Reset Sequence System Considerations
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration Controller Interface Signals
5.6. GMII Signals x
5.6.1. 1G/2.5G/10G MGBASE PCS Only PMA Interface
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
7. Debug Checklist x
7.1. Pre-Debugging Process 7.2. Clock Frequency 7.3. Recommended Reset Handling 7.4. Signals for Signal Tap
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 3 and Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. Debug Checklist
8. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

3.3.2. Reset Sequence

Figure 13. MGBASE Reset Block Diagram
Figure 14. MGBASE Reset Sequence (8-bit Option)
Figure 15. MGBASE Reset Sequence (16-bit Option)
The following describes the reset sequence for MGBASE variants as shown in the figures above:
  • i_rst_n and o_rst_ack_n pair follows a handshake flow as shown in the figure above. i_tx_rst_n and o_tx_rst_ack_n pair, and i_rx_rst_n and o_rx_rst_ack_n pair follow the same flow for TX and RX paths respectively.
  • tx_ready is asserted by the IP several cycles after the i_rst_n is de-asserted. The assertion of tx_ready causes PLL to come out of reset and locked to reference. Locking is signalled by mrphy_pll_lock as shown in the MGBASE Reset Sequence (8-bit Option).
  • In variants with GMII8B adapter, reset, tx_digitalreset, and rx_digitalreset can be asserted at any point. Once the soft logic PLL is locked (mrphy_pll_lock is asserted) or rx_ready is asserted, you can deassert reset, tx_digitalreset, and rx_digitalreset to clear all the soft logic, TX soft logic, or RX soft logic respectively. When the soft logic PLL is locked (mrphy_pll_lock is asserted) or rx_ready goes low, then rx_digitalreset should be applied.
  • In variants without the GMII8B adapter, the IP does not instantiate the soft logic PLL so mrphy_pll_lock signal is not available. tx_digitalreset should be deasserted after tx_ready is asserted, rx_digitalreset should be deasserted after rx_ready is asserted as shown in the MGBASE Reset Sequence (16-bit Option).
Figure 16. MGBASE PCS Only Reset Sequence

The following describe the reset sequence for MGBASE PCS only mode variant as shown in the figure above.

The tx_ready is the ready signal of the external GTS transceiver PHY. It indicates that the TX PMA PLL is locked, the clocks are stable, and the TX PMA is ready for transmission. When the TX PMA goes to reset, the 1G/2.5G/5G/10G Multirate Ethernet PHY tx_digital reset should be asserted after the PMA is ready.

The rx_ready is the ready signal of the external GTS transceiver PHY. It indicates that the RX PMA is locked to the data and the RX PMA is ready for data transfer. The 1G/2.5G/5G/10G Multirate Ethernet PHY RX side modules should be given reset using rx_digital_reset once the GTS transceiver PHY RX is ready.

Refer to GTS Transceiver PHY User Guide for more details.

Figure 17. NBASE and MGBASE 10G Reset Block Diagram
Figure 18. NBASE and MGBASE 10G Reset Sequence
The following steps describe the reset sequence for NBASE as shown in the figure above:
  1. Drive the i_rst_n reset signal high while i_tx_rst_n and i_rx_rst_n reset signals are already deasserted.
  2. The o_rst_ack_n reset signal deasserts. This indicates that the IP core is no longer in the full reset.
    Note: This step doesn't indicate that the IP core is in fully functional state.
    Note: The o_tx_rst_ack_n and o_rx_rst_ack_n reset signals also deassert. The exact sequence and timing is not guaranteed.
  3. The IP core is fully out of reset. Assert o_tx_lanes_stable and o_rx_pcs_ready to indicate that the TX and RX datapaths are ready for use.
  4. Assert the i_tx_rst_n reset signal.
  5. The o_tx_lanes_stable signal deasserts to indicate that the TX datapath is no longer operational.
  6. The o_tx_rst_ack_n signal asserts indicating that the TX datapath is fully in reset. Then, deassert the i_tx_rst_n signal to bring the TX datapath out of the reset.
  7. Assert the i_rx_rst_n reset signal.
  8. The o_rx_pcs_ready signal deasserts to indicate that the RX datapath is no longer operational.
  9. The o_rx_rst_ack_n signal asserts indicating that the RX datapath is fully in reset. Then, deassert the i_rx_rst_n signal to bring the RX datapath out of the reset.
  10. Assert the i_rst_n reset signal.
  11. The o_tx_lanes_stable and o_rx_pcs_ready signals deassert to indicate that TX and RX datapath are no longer operational.
  12. The o_rst_ack_n signals assert to indicate the IP core is fully in reset. To bring the IP core out of the reset, deassert the i_rst_n reset signal.
  13. Assert and deassert tx_digitalreset once the o_tx_lane_stable assert.
  14. Assert and deassert rx_digitalreset once the rx_pcs_ready assert.

System Considerations

  • During the reset, hold the reconfig_reset signal asserted for several valid reconfiguration clock cycles to ensure the Avalon® memory-mapped interface and soft CSRs are fully reset.
  • Access to any Avalon® memory-mapped interface is available while the reconfig_reset signal is low.
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