1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813667
Date 4/01/2024
Document Table of Contents

5.9. Transceiver Status and Reconfiguration Signals

Table 23.  Transceiver Status and Reconfiguration Signals
Signal Name Direction Width Description PHY Configurations
Transceiver status signals
rx_is_lockedtodata Output 1 Asserted when the CDR is locked to the RX data. All
Transceiver reconfiguration signals
reconfig_clk Input 1 Reconfiguration signals connected to the reconfiguration block. All
reconfig_reset Input 1
reconfig_address Input


reconfig_be Input 4
reconfig_write Input 1
reconfig_read Input 1
reconfig_writedata Input 32
reconfig_readdata Output 32
reconfig_readdata_valid Output 1
reconfig_waitrequest Output 1