1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813667
Date 4/01/2024
Document Table of Contents

5.3. Serial Interface Signals

The serial interface connects to an external device.
Table 17.  Serial Interface Signals
Signal Name Direction Width Description PHY Configurations

tx_serial_data (MGBASE-T)/

serial_o_tx_serial (NBASE-T)

Output 1 Transmit serial data. All

rx_serial_data (MGBASE-T)/

serial_i_rx_serial (NBASE-T)

Input 1 Receive serial data All

tx_serial_data_n (MGBASE-T)/

serial_o_tx_serial_n (NBASE-T)

Output 1 Transmit serial data All

rx_serial_data_n (MGBASE-T)/

serial_i_rx_serial_n (NBASE-T)

Input 1 Receive serial data All