1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813667
Date 4/01/2024
Public
Document Table of Contents

6.1. Register Map

Table 26.  Register Map Overview
Address Range Usage Register Width Configuration
0x00–0x1F 1000BASE-X/SGMII 16

2.5G, 1G/2.5G, 10M/100M/1G/2.5G (MGBASE-T)

0x400–0x41F USXGMII 32 10M/100M/1G/2.5G/5G/10G (USXGMII)