1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813667
Date 4/01/2024

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5.11. Dynamic Reconfiguration SRC Signals

Table 25.  Dynamic Reconfiguration SRC Interface Signals
Signal Name Direction Width Description PHY Configurations
o_src_ch_pause_request Output 1 Request pause signal from dynamic reconfiguration controller to reset service. It is required before dynamically modifying group configuration information. MGBASE-T only
o_src_ch_pause_grant Input 1 Indicates that the reset service pause is acknowledged. MGBASE-T only