Low Latency 40G Ethernet IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813652
Date 10/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet IP 2. Low Latency 40G Ethernet IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet IPs 9. Document Revision History for the Low Latency 40G Ethernet IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet IP x
1.1. Low Latency 40G Ethernet IP Supported Features 1.2. Low Latency 40G Ethernet IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Device Family Support 1.2.2. Low Latency 40G Ethernet IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Altera IP 3.2. Installing and Licensing IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet IP Functional Description 4.2. GTS Transceiver Configuration 4.3. Transmitter Datapath 4.4. Receiver Datapath 4.5. Flow Control 4.6. Link Fault Signaling Interface
4.3. Transmitter Datapath x
4.3.1. Transmitter MAC 4.3.2. Transmitter PCS 4.3.3. PMA
4.3.1. Transmitter MAC x
4.3.1.1. Preamble Insertion 4.3.1.2. Frame Padding 4.3.1.3. Inter-Packet Gap Generation and Insertion 4.3.1.4. Frame Check Sequence (CRC-32) Insertion 4.3.1.5. Transmitter Avalon® Streaming Filter
4.4. Receiver Datapath x
4.4.1. Receiver MAC 4.4.2. Receiver PCS
4.4.1. Receiver MAC x
4.4.1.1. IP Core Preamble Processing 4.4.1.2. IP Core CRC Checking and Dynamic Forwarding 4.4.1.3. IP Core Strict SFD Checking 4.4.1.4. Length/Type Field Processing
4.4.1.4. Length/Type Field Processing x
4.4.1.4.1. Frame Type Checking 4.4.1.4.2. Length Checking
4.5. Flow Control x
4.5.1. Transmitter Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
5. Clocking and Reset Requirements x
5.1. Clocks 5.2. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. Transmitter MAC Interface to User Logic 6.2. Receiver MAC Interface to User Logic 6.3. Transmitter PCS Interface to User Logic 6.4. Receiver PCS Interface to User Logic 6.5. GTS Transceivers Signals 6.6. GTS Transceiver Reconfiguration Signals 6.7. Avalon® Memory-Mapped Management Interface 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals 6.10. Clocks 6.11. Flow Control Interface 6.12. GTS Reset Sequencer IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. Transmitter MAC Registers 7.3. Receiver MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet IP
2. Low Latency 40G Ethernet IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet IPs
9. Document Revision History for the Low Latency 40G Ethernet IP User Guide: Agilex™ 5 FPGAs and SoCs

1.1. Low Latency 40G Ethernet IP Supported Features

The Low Latency 40G Ethernet IP supports the following features:

  • Parameterizable through the IP Catalog available with the Quartus® Prime Pro Edition software.
  • Designed to the IEEE 802.3 High Speed Ethernet Standard available on the IEEE website (www.ieee.org).
  • Soft PCS logic that interfaces seamlessly to Altera® FPGA with 10.3125 gigabits per second (Gbps) serial transceivers.
  • Standard XLAUI external interface consisting of FPGA hard serial transceiver lanes operating at 10.3125 Gbps. IP supports the automatic reordering of receiver PCS virtual lanes. The link works even if the transceiver lanes are swapped on the PCB. However, the IP top level serial interface wire tx/rx_serial[n] must be connected to the PMA GTS CH-n.
  • Supports Synchronous Ethernet (SyncE) by providing an optional CDR recovered clock output signal to the device fabric.
  • Avalon® memory-mapped management interface to access the IP control and status registers.
  • Avalon® streaming interface provides data path interface with 128-bit data width that connects to client logic with the start of frame in the most significant byte (MSB).
  • Support for jumbo packets, defined as packets greater than 1500 bytes. The width of the MAX packet size configuration register for the transmitter and receiver is 16-bit. If the packet length is more than the configured size, then IP indicates through oversized error status but the IP does not truncate the packet to the maximum size, the packet is not accepted and transmitted even after the MAX size.
  • XLGMII interface with 128-bit data width that connects to client logic.
  • Receiver CRC removal and pass-through control.
  • Optional transmitter CRC generation and insertion.
  • Receiver CRC checking and error reporting.
  • Receiver and transmitter preamble pass-through option for applications that require proprietary user management information transfer.
  • Optional receiver strict SFD checking per IEEE specification.
  • Transmitter automatic frame padding to meet the 64-byte minimum Ethernet frame length.
  • Received control frame type indication.
  • Unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard.
  • Hardware and software reset control.
  • MAC provides receiver cut-through frame processing, no receiver store-and-forward capability.
  • Deficit idle counter (DIC) to maintain a 12-byte inter-packet gap (IPG) average.
  • Optional fault signaling detects and reports local fault and generates remote fault, with IEEE 802.3ba-2012 Ethernet Standard Clause 66 support.
  • Programmable ready latency of 0 or 3 clock cycles for Avalon® streaming transmitter interface.
  • Optional statistics counters.

For a detailed specification of the Ethernet protocol refer to the IEEE 802.3 Ethernet Standard.

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