Low Latency 40G Ethernet IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813652
Date 10/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet IP 2. Low Latency 40G Ethernet IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet IPs 9. Document Revision History for the Low Latency 40G Ethernet IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet IP x
1.1. Low Latency 40G Ethernet IP Supported Features 1.2. Low Latency 40G Ethernet IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Device Family Support 1.2.2. Low Latency 40G Ethernet IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Altera IP 3.2. Installing and Licensing IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet IP Functional Description 4.2. GTS Transceiver Configuration 4.3. Transmitter Datapath 4.4. Receiver Datapath 4.5. Flow Control 4.6. Link Fault Signaling Interface
4.3. Transmitter Datapath x
4.3.1. Transmitter MAC 4.3.2. Transmitter PCS 4.3.3. PMA
4.3.1. Transmitter MAC x
4.3.1.1. Preamble Insertion 4.3.1.2. Frame Padding 4.3.1.3. Inter-Packet Gap Generation and Insertion 4.3.1.4. Frame Check Sequence (CRC-32) Insertion 4.3.1.5. Transmitter Avalon® Streaming Filter
4.4. Receiver Datapath x
4.4.1. Receiver MAC 4.4.2. Receiver PCS
4.4.1. Receiver MAC x
4.4.1.1. IP Core Preamble Processing 4.4.1.2. IP Core CRC Checking and Dynamic Forwarding 4.4.1.3. IP Core Strict SFD Checking 4.4.1.4. Length/Type Field Processing
4.4.1.4. Length/Type Field Processing x
4.4.1.4.1. Frame Type Checking 4.4.1.4.2. Length Checking
4.5. Flow Control x
4.5.1. Transmitter Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
5. Clocking and Reset Requirements x
5.1. Clocks 5.2. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. Transmitter MAC Interface to User Logic 6.2. Receiver MAC Interface to User Logic 6.3. Transmitter PCS Interface to User Logic 6.4. Receiver PCS Interface to User Logic 6.5. GTS Transceivers Signals 6.6. GTS Transceiver Reconfiguration Signals 6.7. Avalon® Memory-Mapped Management Interface 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals 6.10. Clocks 6.11. Flow Control Interface 6.12. GTS Reset Sequencer IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. Transmitter MAC Registers 7.3. Receiver MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet IP
2. Low Latency 40G Ethernet IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet IPs
9. Document Revision History for the Low Latency 40G Ethernet IP User Guide: Agilex™ 5 FPGAs and SoCs

5.2. Reset Requirements

The reset controller has soft reset signals that are asserted by the CSR and three asynchronous resets that are asserted externally.
Reset Connection
The general reset signals reset the following functions:
  • soft_tx_rst,tx_rst_n: Resets the IP core in the transmitter direction. Resets the transmitter PCS and transmitter MAC. This reset leads to deassertion of the tx_lanes_stable output signal.
  • soft_rx_rst, rx_rst_n: Resets the IP core in the receiver direction. Resets the receiver PCS and receiver MAC. This reset leads to deassertion of the rx_pcs_readyoutput signal.
  • sys_rst, csr_rst_n: Resets the IP core. Resets the transmitter and receiver MACs, PCS, and transceivers.

In addition, the synchronous reconfig_reset signal resets the IP core transceiver reconfiguration interface, an Avalon® memory-mapped interface. Associated clock is the reconfig_clk, which clocks the transceiver reconfiguration interface.

Table 13.  Reset Signals FunctionsIn this table, a tick (√) represents the block is reset by the specified reset signal.
Reset/Module Transmitter MAC Receiver MAC Transmitter Packet Stats Receiver Packet Stats Transmitter PCS Receiver PCS Transmitter PMA Receiver PMA
csr_rst_n/sys_rst √ √ √ √ √ √ √ √
tx_rst_n/soft_tx_rst √       √      
rx_rst_n/soft_rx_rst   √       √    
reconfig_reset                

Reset Sequence or Initialization

The reset sequencing is handled by the core’s reset controller. Asserting a reset on the csr_rst_n signal triggers the reset sequence. When the csr_rst_n reset is asserted, the rx_pcs_ready and tx_lanes_stable signals go low and can only go back high after deasserting the reset.

The CSR register read/write must wait at least 2 clock cycles after the csr_rst_n release or assertion. Altera recommends waiting for 10 clock cycles. You can also reset the transmitter and receiver datapaths independently by toggling tx_rst_n and rx_rst_n respectively.

Figure 10. Reset Sequence
Level Two Title