Low Latency 40G Ethernet IP User Guide: Agilex™ 5 FPGAs and SoCs
6.5. GTS Transceivers Signals
The GTS Transceiver interface is accessible in both MAC, PCS, and PMA and PCS and PMA modes. The GTS Transceiver PHY IP uses four GTS PMA transceivers for the Low Latency 40G Ethernet IP. For more information, refer to the GTS Transceiver PHY User Guide .
The transceivers require a PLL ref clk as an input. The GTS PMA transceiver is configured for a specific setting in order for the successful integration of the existing Low Latency 40G Ethernet MAC and PCS with the GTS PMA transceiver.
Pll_reference clock of GTS PMA transceiver is configured to be 156.25 MHz.
For Sync-E, the recovered clock that is rx_clkout[1] from GTS PMA transceiver is used. This is of frequency 312.5 MHz.
Signal |
Direction |
Width |
Description |
|---|---|---|---|
| tx_serial | Output | 4 | Transmitter transceiver data. Each tx_serial bit becomes two physical pins that form a differential pair. |
| rx_serial | Input | 4 | Receiver transceiver data. Each rx_serial bit becomes two physical pins that form a differential pair. |
| clk_ref_p | Input | 1 | The PLL reference clock used by transmitter and receiver. Input to the clock data recovery (CDR) circuitry in the receiver PMA. |
| cdr_divclk | Output | 1 | Dedicated receiver recover divided clock output from PMA over the local reference clocks pins or dedicated CDR clock output pins. This clock is available only if you turn on Enable SyncE and enable cdr clkout in the IP parameter editor. The normal frequency of cdr_divclk is the input PMA ref clockenb (clk_ref_p/n) divided by 1. The cdr_divclk uses the clk_ref pin for routing. When cdr_divclk is enabled, the number of available ref clocks is reduced to one except in Agilex™ 5 devices. |