Low Latency 40G Ethernet IP User Guide: Agilex™ 5 FPGAs and SoCs
5.1. Clocks
In Agilex™ 5, each transceiver hard IP block (quad) has 4 transceiver lanes can take up to 2 reference clock inputs. One of this ref clock input (local ref clock input) can be configured as output to drive the recovered clock receiver serial line on the dedicated clock routing for SyncE applications.
In Agilex™ 5, each transceiver hard IP block (quad) has one system PLL, the input reference clock to this system pll can be one of the transceiver ref clock inputs or it can be from the HVIO reference clock input. You need to generate the system PLL IP component from IP catalog separately and instantiate in the user design as the system PLL is not part of the Low Latency 40G Ethernet IP. You should configure the system PLL clock output frequency to 322.265625 MHz clock and provide to the Low Latency 40G Ethernet IP on i_system_pll_clk port.
The transmit side clocks (clk_txmac/clk_tx_mii) are derived from the clk_ref_p clock port, the PMA Transmitter PLL takes the clk_ref_p and generates the 312.5 MHz user clock and the transmitter line clocks. The Transmitter PLL is part of the PMA and there is one transmitter PLL per lane/channel. The clk_txmac/clk_tx_mii is stable only when the tx_ready signal is high.
The receive side clocks (clk_rxmac/clk_rx_mii) are derived from the receiver serial recovered clock. The CDR block of the hard IP takes the clk_ref_p as the reference clock and recovers the clk_rxmac/clk_rx_mii from the receiver serial input. The frequency of the clk_rxmac/clk_rx_mii is 312.5 MHz. The clk_rxmac/clk_rx_mii is stable only when the rx_is_lockedtodata signal is high.
The clk_status is the clock used to access the registers of the SIP CSR’s (MAC and PCS), the frequency of this clock should be from 100 MHz to 125 MHz.
The refconfig_clk is the clock used to access the registers of the Hard IP CSR’s , the frequency of this clock should be from 100 MHz to 125 MHz.