Low Latency 40G Ethernet IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813652
Date 10/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet IP 2. Low Latency 40G Ethernet IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet IPs 9. Document Revision History for the Low Latency 40G Ethernet IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet IP x
1.1. Low Latency 40G Ethernet IP Supported Features 1.2. Low Latency 40G Ethernet IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Device Family Support 1.2.2. Low Latency 40G Ethernet IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Altera IP 3.2. Installing and Licensing IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet IP Functional Description 4.2. GTS Transceiver Configuration 4.3. Transmitter Datapath 4.4. Receiver Datapath 4.5. Flow Control 4.6. Link Fault Signaling Interface
4.3. Transmitter Datapath x
4.3.1. Transmitter MAC 4.3.2. Transmitter PCS 4.3.3. PMA
4.3.1. Transmitter MAC x
4.3.1.1. Preamble Insertion 4.3.1.2. Frame Padding 4.3.1.3. Inter-Packet Gap Generation and Insertion 4.3.1.4. Frame Check Sequence (CRC-32) Insertion 4.3.1.5. Transmitter Avalon® Streaming Filter
4.4. Receiver Datapath x
4.4.1. Receiver MAC 4.4.2. Receiver PCS
4.4.1. Receiver MAC x
4.4.1.1. IP Core Preamble Processing 4.4.1.2. IP Core CRC Checking and Dynamic Forwarding 4.4.1.3. IP Core Strict SFD Checking 4.4.1.4. Length/Type Field Processing
4.4.1.4. Length/Type Field Processing x
4.4.1.4.1. Frame Type Checking 4.4.1.4.2. Length Checking
4.5. Flow Control x
4.5.1. Transmitter Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
5. Clocking and Reset Requirements x
5.1. Clocks 5.2. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. Transmitter MAC Interface to User Logic 6.2. Receiver MAC Interface to User Logic 6.3. Transmitter PCS Interface to User Logic 6.4. Receiver PCS Interface to User Logic 6.5. GTS Transceivers Signals 6.6. GTS Transceiver Reconfiguration Signals 6.7. Avalon® Memory-Mapped Management Interface 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals 6.10. Clocks 6.11. Flow Control Interface 6.12. GTS Reset Sequencer IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. Transmitter MAC Registers 7.3. Receiver MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet IP
2. Low Latency 40G Ethernet IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet IPs
9. Document Revision History for the Low Latency 40G Ethernet IP User Guide: Agilex™ 5 FPGAs and SoCs

6.11. Flow Control Interface

These signals are accessible only in MAC, PCS, and PMA mode.

Table 24.  Flow Control Signals

Signal Name

Direction

Width

Description

pause_insert_tx0

 Input QN
These signals are available only if Pause or PFC flow control support is synthesized. Indicates the MAC whether a XON or XOFF Pause or PFC flow control frame should be sent.
  • FCQN = 1 for Pause
  • FCQN = 1 to 8 for PFC

The request for XON/XOFF flow control frame transmission can be done in either 1 or 2-bit request mode (see pause_insert_tx1).

1-bit mode request model:

The following encoding is defined:
  • 0: No request
  • 0 to 1: Generate XOFF request
  • 1: Continue to generate XOFF request
  • 1 to 0: Generate XON request

2-bit mode request model:

Represents the lower bit. Only takes effect when the CSR of 2-bit Flow Control Request mode selects Signal. The following encoding is defined:

  • 00: No request.
  • 01: Generate XON request
  • 10: Generate XOFF request
  • 11: Invalid request
pause_insert_tx1 Input QN

Used in conjunction with pause_insert_tx0 to form a 2-bit request for XON/XOFF flow control frame transmission.

This represents the upper bit of the 2-bit control.
pause_receive_rx Output QN Asserted to indicates receiver pause signal match. The IP asserts bit [n] of this signal when it receives a pause request with an address match, to signal the transmitter MAC to throttle its transmissions from priority queue [n] on the Ethernet link.
Level Two Title