Low Latency 40G Ethernet IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813652
Date 10/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet IP 2. Low Latency 40G Ethernet IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet IPs 9. Document Revision History for the Low Latency 40G Ethernet IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet IP x
1.1. Low Latency 40G Ethernet IP Supported Features 1.2. Low Latency 40G Ethernet IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Device Family Support 1.2.2. Low Latency 40G Ethernet IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Altera IP 3.2. Installing and Licensing IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet IP Functional Description 4.2. GTS Transceiver Configuration 4.3. Transmitter Datapath 4.4. Receiver Datapath 4.5. Flow Control 4.6. Link Fault Signaling Interface
4.3. Transmitter Datapath x
4.3.1. Transmitter MAC 4.3.2. Transmitter PCS 4.3.3. PMA
4.3.1. Transmitter MAC x
4.3.1.1. Preamble Insertion 4.3.1.2. Frame Padding 4.3.1.3. Inter-Packet Gap Generation and Insertion 4.3.1.4. Frame Check Sequence (CRC-32) Insertion 4.3.1.5. Transmitter Avalon® Streaming Filter
4.4. Receiver Datapath x
4.4.1. Receiver MAC 4.4.2. Receiver PCS
4.4.1. Receiver MAC x
4.4.1.1. IP Core Preamble Processing 4.4.1.2. IP Core CRC Checking and Dynamic Forwarding 4.4.1.3. IP Core Strict SFD Checking 4.4.1.4. Length/Type Field Processing
4.4.1.4. Length/Type Field Processing x
4.4.1.4.1. Frame Type Checking 4.4.1.4.2. Length Checking
4.5. Flow Control x
4.5.1. Transmitter Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
5. Clocking and Reset Requirements x
5.1. Clocks 5.2. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. Transmitter MAC Interface to User Logic 6.2. Receiver MAC Interface to User Logic 6.3. Transmitter PCS Interface to User Logic 6.4. Receiver PCS Interface to User Logic 6.5. GTS Transceivers Signals 6.6. GTS Transceiver Reconfiguration Signals 6.7. Avalon® Memory-Mapped Management Interface 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals 6.10. Clocks 6.11. Flow Control Interface 6.12. GTS Reset Sequencer IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. Transmitter MAC Registers 7.3. Receiver MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet IP
2. Low Latency 40G Ethernet IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet IPs
9. Document Revision History for the Low Latency 40G Ethernet IP User Guide: Agilex™ 5 FPGAs and SoCs

2. Low Latency 40G Ethernet IP Parameters

The Low Latency 40G Ethernet IP parameter editor for Agilex™ 5 devices has three tabs, Analog Parameters, Example Design, and an IP tab with the Main as sub-tab.

For information about the Example Design tab, refer to the Low Latency 40G Ethernet IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs .

Table 7.   Low Latency 40G Ethernet IP Parameters: Main Tab
Parameter Range Default Setting Description
General
Protocol Mode PCS and PMA,MAC, PCS, and PMA MAC, PCS, and PMA Select PCS and PMA option for User MAC external to IP or select MAC, PCS and PMA for Integrated MAC in IP.
Protocol speed 40GbE 40GbE Selects the Ethernet data rate.
Ready latency 0, 3 0 Selects the Ready Latency value on the transmitter client interface. Ready Latency is an Avalon® streaming interface property that defines the number of clock cycles of delay from when the IP asserts the l2_tx_ready signal to the clock cycle in which the IP can accept data on the transmitter client interface. Refer to the Avalon® Interface Specifications.

Selecting a latency of 3 eases timing closure at the expense of increased latency for the transmitter datapath. Available in MAC, PCS, and PMA mode only. In PCS and PMA mode, you have a fixed latency of 0 to 9 clocks between ready and valid.
PCS/PMA Options
Enable SyncE Enabled, Disabled Disabled Exposes the receiver recovered clock as an output signal. This feature supports the Synchronous Ethernet standard described in the International Telecommunication Union (ITU) Telecommunication Standardization Sector (ITU-T) G.8261, G.8262, and G.8264 recommendations.
Enable dedicated CDR clock output Enabled, Disabled Disabled When enabled, the recovered clock is routed through the clk_ref pins which uses the clk_ref pin. This option is available only when you enable Enable SyncE .
Enable Clkrx refclk recovery logic Enabled, Disabled Disabled Enable Clkrx refclk recovery related logic and ports (o_refclk_status_bus_out, i_refclk_cmd_bus_in).
  • 0: Disable Clkrx refclk recovery logic
  • 1: Enable Clkrx refclk recovery logic
    Note: This parameter adds recovery logic to restore failing reference clocks.
PHY reference frequency 156.25 MHz, 312.5 MHz, 322.265625 MHz 156.25 MHz Sets the expected incoming PHY clk_ref_p reference frequency. The input clock frequency must match the frequency you specify for this parameter (±100 ppm).
MAC Options
Enable TX CRC insertion Enabled, Disabled Enabled When enabled, transmitter MAC computes and inserts the CRC-32 checksum in the out-going Ethernet frame. When disabled, the transmitter MAC does not compute a 32-bit FCS in the transmitter MAC frame. Instead, the client must provide frames with at least 64 bytes, plus the Frame Check Sequence (FCS).
Enable link fault generation Enabled, Disabled Disabled When enabled, the IP implements link fault signaling as defined in the IEEE 802.3-2012 IEEE Ethernet Standard. The MAC includes a Reconciliation Sublayer (RS) to manage local and remote faults. When enabled, the local RS transmitter logic can transmit remote fault sequences in case of a local fault and can transmit IDLE control words in case of a remote fault.
Enable preamble passthrough Enabled, Disabled Disabled When enabled, the IP is in receiver and transmitter preamble pass-through mode. In receiver preamble pass-through mode, the IP passes the preamble and Start Frame Delimiter (SFD) to the client instead of stripping them out of the Ethernet packet. In transmitter preamble pass-through mode, the client specifies the preamble and provides the SFD to be sent in the Ethernet frame.
Enable MAC stats counters Enabled, Disabled Enabled When enabled, the IP includes statistics counters that characterize transmitter and receiver traffic. The statistics module also supports shadow requests that verify counts by taking snapshots of intermediate results.
Enable Strict SFD check Enabled, Disabled Disabled When enabled, the IP implements strict SFD checking, depending on register settings.
Flow Control Options
Enable MAC flow control Enabled, Disabled Disabled When enabled, the IP implements flow control. When either link partner experiences congestion, the respective transmit control sends pause frames.
Number of queues in priority flow control 1-8 1 Specifies the number of queues used in managing flow control.
Debug Options
Enable Native PHY Debug Master Endpoint Enabled, Disabled Disabled

When enabled, the embedded Native PHY Debug Master Endpoint connects internally to the Avalon® Memory-Mapped Interface. The Native PHY Debug Master Endpoint accesses the reconfiguration space of the transceiver to perform certain tests and debug functions via JTAG using System Console.

Analog Parameters

For more information, refer to GTS Transceiver PHY User Guide.

Figure 2. Analog Parameters tab
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