Cyclone® V to Agilex™ 5 Device Migration Guide

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ID 787947
Date 1/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

2.3.3. Active Serial (AS) Configuration

This topic describes key differences in Active Serial (AS) configuration between Cyclone® V and Agilex™ 5 devices.

Table 4.  AS Configuration Pin Differences
Configuration Pin Name – Cyclone® V Configuration Pin Name – Agilex™ 5 Notes
DCLK SDM_IO2 (AS_CLK) When using the internal oscillator in the AS mode, the AS_CLK runs in the range of 57 - 115 based on the AS_CLK selection. If you provide a 25 MHz, 100 MHz, or 125 MHz clock to the OSC_CLK_1 pin, the AS_CLK can run up to 166 MHz.

AS_DATA0_ASDO

AS_DATA[3:1]

SDM_IO4 (AS_DATA0)

SDM_IO6 (AS_DATA3)

SDM_IO3 (AS_DATA2)

SDM_IO1 (AS_DATA1)

Agilex™ variants no longer support AS x1. They only support AS x4.
nCSO

SDM_IO8 (AS_nCSO3)

SDM_IO7 (AS_nCSO2)

SDM_IO9 (AS_nCSO1)

SDM_IO5 (AS_nCSO0)

Agilex™ devices support up to four cascaded configuration devices.
Not supported SDM_IO15 (AS_nRST) Quad SPI (QSPI) reset pin must be connected to AS_nRST pin and fully controlled by SDM. Do not connect the QSPI reset pin to any external host.

The following are other key difference to consider for AS configuration:

  • Agilex™ 5 device supports only the AS x4 mode and not support the AS x1 configuration mode.
  • For JTAG Indirect Configuration File (.jic) programming, an Agilex™ 5 device uses a helper image to provide the SDM firmware and Cyclone® V requires the Serial Flash Loader IP to facilitate programming of flash over JTAG. Use the Programming File Generator tool to generate the configuration image for Agilex™ 5 device and Convert Programming Files tool for Cyclone® V device.
  • For Programmer Object File (POF) programming via AS pins, set MSEL to the JTAG mode to tristate the AS interface.
  • AS configuration does not retry once the configuration fails. Toggle nCONFIG to restart the configuration if necessary.
  • Generic QSPI flash support is enabled to support any QSPI flash that supports the Serial Flash Discovery Parameter (SFDP) standard and dedicated reset pin. With Agilex™ 5 device, you can use the QSPI flash that supports 3-byte or 3-byte and 4-byte addressing. QSPI flash that supports 3-byte and 4-byte addressing must by default support 3-byte addressing.
  • Input DATA setup or hold time specification in Cyclone® V AS timing specifications no longer applies to Agilex™ 5 device. Hence, the timing analysis for the input DATA setup or hold time analysis in Agilex™ 5 device is not required. In Agilex™ 5, you must meet the total external propagation delay on AS signals (Text_delay) specification to meet the input DATA setup or hold time required by the AS_DATA pins. For example:

Cyclone® V AS timing specification:

Text_delay specification in Agilex™ 5 AS timing specification:

For additional information, refer to the "Active Serial Configuration" section in the Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration and Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs.

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