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2.8.1. HSIO Bank
The guidelines in this topic apply when switching your FPGA and board design from a Cyclone® V device to an Agilex™ 5 device.
I/O Bank Architecture and Resources
The FPGA I/O bank in the Cyclone® V device is row and column-oriented, with up to 10 I/O bank count per device. The On-Chip Termination (OCT) calibration block and PLL are located at the corner and center between FPGA I/O banks and can be shared across banks. For more information about Cyclone® V FPGA I/O bank orientation and shared resources, refer to the Cyclone V Device Handbook: Volume 1: Device Interfaces and Integration.
The HSIO bank in the Agilex™ 5 device is located at the top and bottom rows of the device. Each HSIO bank contains two sub-banks. Each sub-bank is further divided into four I/O lanes with 12 I/O pins per lane. Each HSIO bank has its individual PLL, clock network, OCT calibration block, and Hard Memory Controller (HMC) resources. For more information about Agilex™ 5 FPGA I/O bank orientation and shared resources, refer to the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs .
Due to the architectural differences between Cyclone® V and Agilex™ 5 devices, the I/O design guidelines differ. When switching from the Cyclone® V FPGA I/O to Agilex™ 5 HSIO bank, you must replan your FPGA pin and resource sharing. Refer to the related information in the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs .
VCCIO and I/O Predriver Voltage Supplies
Cyclone® V FPGA I/O bank supports a wider VCCIO range, while Agilex™ 5 HSIO bank targets a lower VCCIO supply range. The I/O pre-driver voltage supply is lowered in the Agilex™ 5 device when compared to the Cyclone® V device.
The following table lists the VCCIO and I/O pre-driver support for Agilex™ 5 and Cyclone® V devices:
Device | VCCIO Support | VCCPD/VCCPT |
---|---|---|
Cyclone® V | 1.2 V / 1.25 V / 1.35 V / 1.5 V / 1.8 V / 2.5 V / 3.0V / 3.3V | 2.5 V / 3.0 V / 3.3 V |
Agilex™ 5 | 1.0 V / 1.05 V / 1.1 V / 1.2 V / 1.3 V | 1.8 V |
The VCCIO granularity for the Cyclone® V device is per bank basis, while Agilex™ 5 device is per sub-bank. You must replan your I/O standard and pin allocation per interface and the board design voltage supplies when switching from Cyclone® V FPGA I/O to Agilex™ 5 HSIO bank. Agilex™ 5 device does not support multi-volt I/O as opposed to the Cyclone® V device.
I/O Types and Standards
While the I/O types that Cyclone® V devices support are similar to the Agilex™ 5 device, the I/O standard support list differs between these two devices. The following table lists the I/O standard comparison between Cyclone® V and Agilex™ 5 devices:
I/O Types | Cyclone® V I/O Standards | Agilex™ 5 HSIO I/O Standards |
---|---|---|
Single-ended non-voltage referenced |
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Note: 1.8 V to 3.3 V are supported with HVIO. Refer to HVIO Bank for more information.
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Single-ended and pseudo-differential voltage-referenced |
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True differential |
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Due to the differences in I/O standard support between Cyclone® V and Agilex™ 5 devices, the electrical specification and on-board termination between these devices differ. You must replan your FPGA pin assignments and board design when switching from Cyclone® V FPGA I/O to Agilex™ 5 HSIO bank to ensure that the upstream and downstream device can interface with the Agilex™ 5 HSIO bank.
Refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet for more information about the electrical specification for each I/O standard and the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs for more information about the on-board termination recommendation.