Cyclone® V to Agilex™ 5 Device Migration Guide

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ID 787947
Date 1/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

3.1. Overview

Due to the difference in the devices supported in different Quartus® Prime editions, you cannot directly migrate Cyclone® V designs from the Quartus® Prime Standard Edition software to Quartus® Prime Pro Edition software for the designs to target an Agilex™ 5 device.

The following table lists main differences between Cyclone® V and Agilex™ 5 designs in the Quartus® Prime software:

Table 32.   Cyclone® V and Agilex™ 5 Design Differences
  Cyclone® V Devices Agilex™ 5 Devices
Quartus® Prime Software Edition Supported only by Quartus® Prime Standard Edition and Quartus® Prime Lite Edition software. Supported only by the Quartus® Prime Pro Edition software.
Quartus® Prime Software Features Quartus® Prime Standard Edition and Quartus® Prime Lite Edition software lack the unique features of Quartus® Prime Pro Edition. Quartus® Prime Pro Edition supports the following unique features:
  • Compile using block-based and hyper-aware design flows.
  • Run Fitter stages incrementally and optimize using detailed reports generated for each stage.
Note:
  • For a quick comparison of Quartus® Prime Standard Edition and Quartus® Prime Pro Edition features, refer to the "Selecting an Quartus® Prime Software Edition" topic in the Quartus® Prime Pro Edition User Guide: Getting Started.
  • You cannot revert designs migrated from Quartus® Prime Standard Edition to Quartus® Prime Pro Edition back to Quartus® Prime Standard Edition. Hence, before modifying your Quartus® Prime Standard Edition project for migration, click Project > Archive Project to save a copy of your original project. For more information about the design migration from Quartus® Prime Standard Edition or Quartus® Prime Lite Edition to Quartus® Prime Pro Edition, refer to the "Migrating to Quartus® Prime Pro Edition" topic in the Quartus® Prime Pro Edition User Guide: Getting Started.

The following table lists key differences between the Platform Designer system in Quartus® Prime Pro Edition and Quartus® Prime Standard Edition based on the supported features and on how it handles IP files:

Table 33.  Differences Between the Platform Designer System
Quartus® Prime Standard Edition Platform Designer Quartus® Prime Pro Edition Platform Designer
Hierarchical isolation is not supported. Introduces hierarchical isolation between system interconnect and IP components.
Does not have generic IP components. Platform Designer Pro can define generic IP components—instantiate generic IP components without an HDL implementation.
Saves both component instantiation and system interconnects in a .qsys file. When integrating a Platform Designer system to an Quartus® Prime project, you must include only a single Quartus® Prime IP file (.qip). Requires including the .qsys file along with a list of .ip files associated with your Platform Designer project. The Quartus® Prime Pro Edition software manages this for you after you save your Platform Designer project.

For more information about the unique Platform Designer capabilities in Quartus® Prime Pro Edition, refer to the Quartus® Prime Pro Edition User Guide: Platform Designer.

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