Cyclone® V to Agilex™ 5 Device Migration Guide

Download PDF
ID 787947
Date 1/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Device Migration Considerations 3. Intel Quartus Prime and Platform Designer Migration Guidelines 4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide
2. Device Migration Considerations x
2.1. Device Footprint 2.2. Power Management 2.3. Configuration 2.4. Design Security Differences 2.5. Logic Elements and Embedded Memory 2.6. PLL and Clock Network 2.7. Digital Signal Processing (DSP) 2.8. I/O Interfaces 2.9. LVDS SERDES Interface 2.10. Sensor Monitoring System 2.11. MIPI D-PHY Interface 2.12. External Memory Interface (EMIF) 2.13. Hard Processor System (HPS) 2.14. Transceiver and Serial Protocols 2.15. PCIe Interface 2.16. Ethernet Interface
2.3. Configuration x
2.3.1. General Configuration Pin and Sequences 2.3.2. Device Configuration and the Secure Device Manager (SDM) 2.3.3. Active Serial (AS) Configuration 2.3.4. Avalon® -ST Configuration 2.3.5. JTAG Configuration 2.3.6. Configuration via Protocol (CvP) 2.3.7. QSPI Flash Access and Remote System Upgrade Feature 2.3.8. SEU Features 2.3.9. Configuration File Format Differences
2.8. I/O Interfaces x
2.8.1. HSIO Bank 2.8.2. HPS I/O Bank 2.8.3. SDM I/O Bank 2.8.4. HVIO Bank
2.13. Hard Processor System (HPS) x
2.13.1. HPS Boot Flows
2.14. Transceiver and Serial Protocols x
2.14.1. PMA Architecture 2.14.2. PCS Architecture 2.14.3. Transceiver Clocking 2.14.4. Transceiver Reset
3. Intel Quartus Prime and Platform Designer Migration Guidelines x
3.1. Overview 3.2. IP Comparison Between Cyclone® V and Agilex™ 5 Devices 3.3. Upgrading IP Cores and Platform Designer Systems 3.4. RTL Compliance
3.3. Upgrading IP Cores and Platform Designer Systems x
3.3.1. Upgrading IP Cores via Quartus® Prime Software Project 3.3.2. Upgrading IP Cores in Platform Designer 3.3.3. Migrating IP Cores to a Different Device
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device x
4.1. Prerequisites 4.2. Downloading and Extracting the Design Example 4.3. Migrating the Design Example
4.3. Migrating the Design Example x
4.3.1. Restoring an Archived Cyclone® V Design in the QAR Format 4.3.2. Specifying an Agilex™ 5 Device 4.3.3. Upgrading IP Cores 4.3.4. Establishing Connections 4.3.5. Compiling the Design
1. Overview
2. Device Migration Considerations
3. Intel Quartus Prime and Platform Designer Migration Guidelines
4. Example: Design Migration from Cyclone® V to Intel Agilex® 5 Device
A. Document Revision History for Cyclone® V to Agilex™ 5 Device Migration Guide

2.12. External Memory Interface (EMIF)

External Memory Interface (EMIF) migration between Cyclone® V and Agilex™ 5 E-series devices is not possible because of the architectural differences between the two device families.

Memory standard support in Cyclone® V and Agilex™ 5 devices are mutually different in each other. You must select memory protocol that Agilex™ 5 devices support when planning to migrate from Cyclone® V devices. You must also consider either migrating to Agilex™ 5 E-series devices that support only component memory type or Agilex™ 5 D-series devices that support both Dual In-Line Memory Modules (DIMMs) and Component memory type.

For controller interface, Cyclone® V devices support Avalon® memory-mapped interface protocol while Agilex™ 5 devices support AXI protocol.

Supported External Memory Standards

The following table shows the supported memory standard for Cyclone® V and Agilex™ 5 devices:

Table 21.  Supported Memory Standards
Memory Standard Cyclone® V Agilex™ 5 E-Series Device Group A Agilex™ 5 E-Series Device Group B Agilex™ 5 D-Series
DDR5 Not supported Supported Not supported Supported
DDR4 Not supported Supported Supported Supported
DDR3 Supported Not supported Not supported Not supported
DDR2 Supported Not supported Not supported Not supported
LPDDR5 Not supported Supported Supported Supported
LPDDR4 Not supported Supported Supported Supported
LPDDR2 Supported Not supported Not supported Not supported
QDR-IV Not supported Not supported Not supported Supported
Related Information
Level Two Title