High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP User Guide

ID 773264
Date 4/29/2024
Document Table of Contents

5.2.2. Requirement and Timing of the hbm_reset_n Signal

The hbm_reset_n signal is a user-initiated reset which resets the entire UIB sub-system, including the controller, PHY, and HBM2E DRAM.

The following waveform illustrates the timing associated with the hbm_reset_n signal.

Figure 15.  hbm_reset_n Timing

The following rules apply to the hbm_reset_n signal:

  • To assert hbm_reset_n, you should drive it from a high to low state and hold it low for at least one core clock cycle, and then transition the signal from low to high state.
  • The HBM system remains in reset if you hold hbm_reset_n low. Reset is completed only after you de-assert hbm_reset_n from low to high state.
  • You can assert hbm_reset_n again after hbm_reset_in_prog goes low (reset completed). Any assertion of hbm_reset_n while the reset is in progress is ignored.
  • The local_cal_success signal de-asserts for several core clock cycles after the reset sequence begins and asserts when reset is completed. Calibration does not occur when the IP reset configuration is set to HBM only reset; calibration occurs when you set IP reset configuration to Reset with calibration.
  • You can start new traffic on the AXI interface after hbm_reset_in_prog is low and local_cal_success is high.