High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP User Guide

ID 773264
Date 4/29/2024
Document Table of Contents

6.1.4. High Bandwidth Memory (HBM2E) Interface FPGA IP Timing

The maximum HBM2E memory interface frequency is based on the Agilex™ 7 device speed grade. The hard memory NoC operating frequency is fixed, and depends only on the device speed grade. The maximum core-to-NoC interface frequency is limited by the frequency at which the core logic can meet timing.

For the best HBM2E efficiency, ensure that your user logic follows best design practices. Take care to avoid combinational paths between the AXI master and slave input and output signals. Add pipeline registers as necessary and reduce logic levels in timing-critical paths to successfully meet core timing requirements.