High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP User Guide

ID 773264
Date 4/29/2024
Document Table of Contents

6.2. High Bandwidth Memory (HBM2E) Interface FPGA IP System Performance

This topic provides recommendations for achieving optimal system performance with HBM2E IP.

Initiator-to-target NoC mapping

  • 1-to-1: Choose this 1-to-1 NoC target to initiator connectivity for the designs that need one master accessing full address range of the single HBM2E pseudo-channel.
  • 16X16 cross bar: Choose this connectivity for the designs that have multiple master accessing the same HBM2E pseudo-channels.

Initiator placements

  • If initiators and targets are to be connected one-to-one, place the initiators closest to the targets that they connect to.
  • For a design containing sixteen initiators, select nine initiators from the three sectors directly beneath the UIB, and three initiators from the sector adjacent to the UIB on the left, and four initiators from the sectors adjacent to UIB on the right.

Number of Initiators

Your HBM2E design requires 16 initiators (one initiator per target) to achieve maximum bandwidth considering full memory access.

Fabric NoC

You should use fabric NoC in your design in case your application requires increased read bandwidth. The Fabric NoC option provides a 512-bit wide AXI4 read data width. Refer to the Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide for detailed information on fabric NoC. For more information on different fabric NoC configurations, refer to the HBM2E Design Example UG.

512-bit symmetric data path

512-bit symmetric data path: Choose 512-bit wide Datapath in your HBM2E IP design to maximize your system performance. When you choose this option the user clock of read and write AXI channels are independent from the NoC initiator hardware clock. You can run the NoC Initiator hardware clock as high as possible and the 512-bit wide core clock frequency can be relatively lower. For detailed implementation of the 512-bit symmetric Datapath configuration, refer to the Fabric NoC section of the High Bandwidth Memory (HBM2E) Interfaces Agilex 7 M-Series FPGA IP Design Example User Guide .