High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP User Guide

ID 773264
Date 4/29/2024
Document Table of Contents

5.3.2. AXI Read Transaction

Read Address

The AXI master asserts the ARVALID signal only when it drives a valid Read address accompanying control signals. Once asserted, ARVALID must remain asserted until the rising clock edge after the AXI slave asserts the ARREADY signal. If ARREADY is high, the AXI slave accepts a valid address that is presented to it. ARUSER, the user signal for auto precharge must be presented at the same time as ARADDR.

Read Data Channel

The slave asserts the RVALID signal when it drives valid read data to the user logic. The master interface uses the RREADY signal to indicate that it accepts the data. The state of RREADY can be always held high, if the master is always able to accept read data. The slave asserts the RLAST signal when it is driving the final read transfer in the burst.

The figure below describes the AXI transaction corresponding to an HBM pseudo-BL8 Read transaction. The AXI master asserts the Read address (RA0) in T1 using transaction ID ARID0, the slave ARREADY is already asserted, the READ command is accepted. The slave provides the Read Data back to the master after processing the read command and obtaining the requested data. The slave presents the Read data in clock cycle Ta. The Read transaction ID (RID) provided by the slave corresponds to the Read Address ID (ARID). The second half of the 64 bytes returned by a pseudo-BL8 read are presented in clock cycle Ta+1, and RLAST is asserted to indicate that this is the last read response beat of the AXI transaction.

Figure 19. AXI Read Transaction – Using Pseudo-BL8 Memory Read Transaction