High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP User Guide

ID 773264
Date 4/29/2024
Document Table of Contents

2.3. Agilex™ 7 HBM2E Features

Agilex™ 7 M-Series FPGAs offer the following HBM2E features.
  • Supports two configurations: 4H/8GB and 8H/16GB.
  • Transfer rate up to 3.2 GT/s for the fastest device speed grade.
  • 2GB capacity per DRAM die.
  • Supports one to eight HBM2E channels per HBM2E interface in the Pseudo Channel mode.
  • Each HBM2E channel supports a 128-bit DDR data bus, with optional ECC support.
  • Pseudo Channel mode divides each channel into two individual 64-bit I/O pseudo-channels. The two pseudo-channels operate semi-independently; they share the channel’s row and column command bus as well as CK and CKE inputs, but they decode and execute commands individually. Address BA4 directs commands to either pseudo-channel 0 (BA4 = 0) or pseudo-channel 1 (BA4 = 1), offering unique address space to each pseudo-channel. Pseudo Channel mode requires that the burst length for DRAM transactions is set to 4.
  • Data referenced to strobes RDQS_t / RDQS_c and WDQS_t / WDQS_c, one strobe pair per 32 DQs.
  • Differential clock inputs (CK_t / CK_c). Unterminated data/address/cmd/clk interfaces.
  • DDR commands entered on each positive CK_t and CK_c edge. Row Activate commands require two memory cycles; all other commands are single-cycle commands.
  • Supports command, write data and read data parity.
  • Support for bank grouping.
  • Support for data bus inversion.
  • 64-bit data per pseudo-channel. Eight additional data bits are available per pseudo-channel; you can use these data bits for any of the following:
    • ECC. The ECC scheme implemented is single-bit error correction with double-bit error detection (SECDEC). This includes 8 bits of ECC code (also known as syndrome).
    • Data mask (DM). The data mask for masking write data per byte.
    • User-defined data
    • Can be left unused.
  • I/O voltage of 1.2V and DRAM core voltage of 1.2V.