High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP User Guide

ID 773264
Date 4/29/2024
Document Table of Contents

2. Introduction to High Bandwidth Memory

High Bandwidth Memory (HBM) is a JEDEC specification (JESD-235) for a wide, high bandwidth memory device. The next generation of High Bandwidth Memory, HBM2E, is defined in JEDEC specification JESD-235C. The HBM2E implementation in Agilex™ 7 M-Series devices complies with JESD-235C.

The High Bandwidth Memory DRAM is tightly coupled to the host die with a distributed interface. The interface is divided into channels, each completely independent of one another. Each memory channel interface has a 128-bit data bus, operating at DDR data rates.