Parameterizable Macros for Intel FPGAs User Guide

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ID 772350
Date 6/26/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Parameterizable Macros for Intel FPGAs Overview 3. Dual-Port Random Access Memory (RAM) Parameterizable Macros 4. FIFO Parameterizable Macros 5. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide 6. Parameterizable Macros for Intel FPGAs User Guide Archives
2. Parameterizable Macros for Intel FPGAs Overview x
2.1. Available Parameterizable Macros for Intel FPGAs 2.2. Inserting HDL Code from Parameterizable Macros Template
3. Dual-Port Random Access Memory (RAM) Parameterizable Macros x
3.1. Simple Dual-Port RAM Parameterizable Macros 3.2. True Dual-Port RAM Parameterizable Macros
3.1. Simple Dual-Port RAM Parameterizable Macros x
3.1.1. Simple Dual-Port RAM Port Descriptions 3.1.2. Simple Dual-Port RAM Parameters 3.1.3. Simple Dual-Port RAM VHDL Instantiation Template 3.1.4. Simple Dual-Port RAM Verilog Instantiation Template
3.2. True Dual-Port RAM Parameterizable Macros x
3.2.1. True Dual-Port RAM Port Descriptions 3.2.2. True Dual-Port RAM Parameters 3.2.3. True Dual-Port RAM VHDL Instantiation Template 3.2.4. True Dual-Port RAM Verilog Instantiation Template
4. FIFO Parameterizable Macros x
4.1. Asynchronous FIFO Parameterizable Macros 4.2. Synchronous FIFO Parameterizable Macros
4.1. Asynchronous FIFO Parameterizable Macros x
4.1.1. Asynchronous FIFO Port Descriptions 4.1.2. Asynchronous FIFO Parameters 4.1.3. Asynchronous FIFO VHDL Instantiation Template 4.1.4. Asynchronous FIFO Verilog Instantiation Template
4.2. Synchronous FIFO Parameterizable Macros x
4.2.1. Synchronous FIFO Port Descriptions 4.2.2. Synchronous FIFO Parameters 4.2.3. Synchronous FIFO VHDL Instantiation Template 4.2.4. Synchronous FIFO Verilog Instantiation Template
1. Answers to Top FAQs
2. Parameterizable Macros for Intel FPGAs Overview
3. Dual-Port Random Access Memory (RAM) Parameterizable Macros
4. FIFO Parameterizable Macros
5. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
6. Parameterizable Macros for Intel FPGAs User Guide Archives

3.1.2. Simple Dual-Port RAM Parameters

Table 2.  Simple Dual-Port RAM Parameterizable Macros Parameters
Name Allowed Values Description
ADDR_ACLR_B

NONE

CLEAR0

Clear for read address registers at Port B.
ADDR_REG_CLK_B

CLOCK1

CLOCK0

Clock choice for address registers at Port B.
ADDR_WIDTH_A Device and DATA_WIDTH_A dependent Specifies the width of the usedw port. The default value is 11.
ADDR_WIDTH_B Device and DATA_WIDTH_B dependent Specifies the width of the usedw port. The default value is 11.
RDCONTROL_REG_B

CLOCK1

CLOCK0

Clock choice for read control registers at Port B.
BYTEENA_REG_B

CLOCK1

CLOCK0

Clock for byte enable registers at Port B.
BYTE_EN_WIDTH_A 1 Width of the byte enable bus at Port A. The width for BYTE_EN_WIDTH_A should be equal to DATA_WIDTH_A divided by BYTE_SIZE.
BYTE_SIZE

5

8

9

10

Specifies the size of the byte for byte-enable mode.
OUT_DATA_ACLR_B

CLEAR1

CLEAR0

NONE

Asynchronous clear for data output registers at Port B. When OUT_DATA_REG_CLK_B is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch.
OUT_DATA_REG_CLK_B

UNREGISTERED

CLOCK1

CLOCK0

Clock choice for data output registers at Port B.
OUT_DATA_SCLR_B

NONE

SCLEAR

Synchronous clear for data output registers at Port B. When OUT_DATA_REG_CLK_B is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch.
DATA_WIDTH_A Device and ADDR_WIDTH_A dependent Specifies the width of the data and q ports. The default value is 8.
DATA_WIDTH_B Device and ADDR_WIDTH_A dependent Specifies the width of the data and q ports. The default value is 8.
INIT_FILE

*.mif

*.hex

Specifies the initialization file.
INIT_FILE_LAYOUT

PORT_A

PORT_B 		Specifies the layout of the initialization file.
IN_CLOCK_EN_A

NORMAL

BYPASS

Specifies the clock enable for the input registers of Port A.
IN_CLOCK_EN_B

NORMAL

BYPASS

Specifies the clock enable for the input registers of Port B.
MAX_DEPTH 2048 Specifies the depth of the RAM slices.
OUT_CLOCK_EN_B

NORMAL

BYPASS

Specifies the clock enable for the output registers of Port B.
READ_DURING_WRITE_MODE_MIXED_PORTS

DONT_CARE

NEW_DATA

OLD_DATA

The behavior of read-during-write mode in mixed-ports.

  • The value of NEW_DATA is supported only when the read address and output data are registered by the write clock in the MLAB mode.
  • The value of DONT_CARE is supported only in the MLAB mode.
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