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1. Answers to Top FAQs
2. Parameterizable Macros for Intel FPGAs Overview
3. Dual-Port Random Access Memory (RAM) Parameterizable Macros
4. FIFO Parameterizable Macros
5. Document Revision History for the Parameterizable Macros for Intel FPGAs User Guide
6. Parameterizable Macros for Intel FPGAs User Guide Archives
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3.1.3. Simple Dual-Port RAM VHDL Instantiation Template
Simple Dual-Port RAM VHDL Instantiation Template
-- Documentation : -- https://www.intel.com/content/www/us/en/docs/programmable/772350/ -- Macro Location : -- $QUARTUS_ROOTDIR/eda/sim_lib/altera_lnsim_components.vhd -- Add the library and use clauses before the design unit declaration library altera_lnsim; use altera_lnsim.altera_lnsim_components.all; -- Instantiating SIMPLE_DUAL_PORT_RAM <instance_name> : SIMPLE_DUAL_PORT_RAM generic map ( IN_CLOCK_EN_A => "NORMAL", IN_CLOCK_EN_B => "NORMAL", OUT_CLOCK_EN_B => "NORMAL", DATA_WIDTH_A => 8, ADDR_WIDTH_A => 11, BYTE_EN_WIDTH_A => 1, DATA_WIDTH_B => 8, ADDR_WIDTH_B => 11, OUT_DATA_REG_CLK_B => "UNREGISTERED", ADDR_REG_CLK_B => "CLOCK0", OUT_DATA_ACLR_B => "NONE", OUT_DATA_SCLR_B => "NONE", ADDR_ACLR_B => "NONE", READ_DURING_WRITE_MODE_MIXED_PORTS => "DONT_CARE", INIT_FILE => "", INIT_FILE_LAYOUT => "PORT_A", MAX_DEPTH => 2048, RDCONTROL_REG_B => "CLOCK0", BYTEENA_REG_B => "CLOCK0", BYTE_SIZE => 8 ) port map ( clock0 => _connected_to_clock0_, -- input, width = 1 clock1 => _connected_to_clock1_, -- input, width = 1 data_a => _connected_to_data_a_, -- input, width = DATA_WIDTH_A address_a => _connected_to_address_a_, -- input, width = ADDR_WIDTH_A address_b => _connected_to_address_b_, -- input, width = ADDR_WIDTH_B wren_a => _connected_to_wren_a_, -- input, width = 1 rden_b => _connected_to_rden_b_, -- input, width = 1 clocken0 => _connected_to_clocken0_, -- input, width = 1 clocken1 => _connected_to_clocken1_, -- input, width = 1 aclr0 => _connected_to_aclr0_, -- input, width = 1 aclr1 => _connected_to_aclr1_, -- input, width = 1 sclr => _connected_to_sclr_, -- input, width = 1 byteena_a => _connected_to_byteena_a_, -- input, width = BYTE_EN_WIDTH_A addressstall_a => _connected_to_addressstall_a_,-- input, width = 1 addressstall_b => _connected_to_addressstall_b_,-- input, width = 1 q_b => _connected_to_q_b_ -- output, width = DATA_WIDTH_B );