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2. Parameterizable Macros for Intel FPGAs Overview
3. Dual-Port Random Access Memory (RAM) Parameterizable Macros
4. FIFO Parameterizable Macros
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4.1.3. Asynchronous FIFO VHDL Instantiation Template
ASYNC_FIFO VHDL Instantiation Template
-- Quartus Prime Parameterizable Macro Template -- ASYNC FIFO -- Documentation : -- https://www.intel.com/content/www/us/en/docs/programmable/772350/ -- Macro Location : -- $QUARTUS_ROOTDIR/eda/sim_lib/altera_lnsim_components.vhd -- Add the library and use clauses before the design unit declaration library altera_lnsim; use altera_lnsim.altera_lnsim_components.all; -- Instantiating ASYNC_FIFO <instance_name> : ASYNC_FIFO generic map ( DATA_WIDTH_A => 8, ADDR_WIDTH_A => 11, DATA_WIDTH_B => 8, ADDR_WIDTH_B => 11, RDSYNC_DELAYPIPE => 2, WRSYNC_DELAYPIPE => 2, ENABLE_SHOWAHEAD => "OFF", UNDERFLOW_CHECKING => "ON", OVERFLOW_CHECKING => "ON", ADD_USEDW_MSB_BIT => "OFF", WRITE_ACLR_SYNCH => "OFF", READ_ACLR_SYNCH => "OFF", ADD_RAM_OUTPUT_REGISTER => "OFF", MAXIMUM_DEPTH => 2048, BYTE_EN_WIDTH => 1, BYTE_SIZE => 8 ) port map ( data => _connected_to_data_, -- input, width = DATA_WIDTH_A rdclk => _connected_to_rdclk_, -- input, width = 1 wrclk => _connected_to_wrclk_, -- input, width = 1 aclr => _connected_to_aclr_, -- input, width = 1 rdreq => _connected_to_rdreq_, -- input, width = 1 wrreq => _connected_to_wrreq_, -- input, width = 1 byteena => _connected_to_byteena_, -- input, width = BYTE_EN_WIDTH rdfull => _connected_to_rdfull_, -- output, width = 1 wrfull => _connected_to_wrfull_, -- output, width = 1 rdempty => _connected_to_rdempty_, -- output, width = 1 wrempty => _connected_to_wrempty_, -- output, width = 1 rdusedw => _connected_to_rdusedw_, -- output, width = ADDR_WIDTH_B wrusedw => _connected_to_wrusedw_, -- output, width = ADDR_WIDTH_A q => _connected_to_q_ -- output, width = DATA_WIDTH_B );