Parameterizable Macros for Intel FPGAs User Guide

ID 772350
Date 6/26/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.2. Synchronous FIFO Parameterizable Macros

For sync_fifo/SYNC_FIFO, the read and write signals are synchronized to the same clock. Memory used in sync_fifo/SYNC_FIFO is simple dual port RAM.

Figure 5. Synchronous FIFO Block Diagram