Agilex™ 7 Clocking and PLL User Guide: M-Series

ID 769001
Date 4/01/2024
Document Table of Contents Reset

The reset signal port of the IP core for I/O PLL is reset.

The reset signal is the reset or resynchronization input for each I/O PLL. The device input pins or internal logic can drive these input signals.

When the reset signal is driven high, the I/O PLL counters reset, clearing the I/O PLL output and placing the I/O PLL out-of-lock. The VCO is then set back to its nominal setting. When the reset signal is driven low again, the I/O PLL resynchronizes to its input clock source as it re-locks.

You must assert the reset signal every time the I/O PLL loses lock to guarantee the correct phase relationship between the I/O PLL input and output clocks. You can set up the I/O PLL to automatically reset (self-reset) after a loss-of-lock condition using the Quartus® Prime parameter editor.

You must include the reset signal if either of the following conditions is true:

  • I/O PLL reconfiguration or clock switchover is enabled in the design.
  • Phase relationships between the I/O PLL input and output clocks must be maintained after a loss-of-lock condition.

Reset the I/O PLL after the input clock is stable and within specifications, even when the self-reset feature is enabled, if either one of the following conditions occur:

  • The input clock to the I/O PLL is not toggling or is unstable when the FPGA transitions into user mode.
  • The I/O PLL cannot lock to the reference clock after reconfiguring the I/O PLL.