Agilex™ 7 Clocking and PLL User Guide: M-Series

ID 769001
Date 4/01/2024
Document Table of Contents

2.2.4. PLL Architecture

Figure 10. I/O Bank I/O PLL High-Level Block Diagram for M-Series Devices
  • The dedicated clock inputs can feed only one PLL via the dedicated clock path. To feed the second PLL, the clock must be routed onto a global clock network.
  • If a global reference clock source is required, this clock must be promoted using the Assignment Editor to promote the PLL refclk to a global signal.