Agilex™ 7 Clocking and PLL User Guide: M-Series

ID 769001
Date 4/01/2024
Document Table of Contents

3.1. Guidelines: Clock Switchover

When implementing clock switchover in M-Series I/O PLLs, refer to the following guidelines:

  • Automatic clock switchover requires that the inclk0 and inclk1 frequencies are within 20% of each other. Failing to meet this requirement causes the clkbad0 and clkbad1 signals to not function properly.
  • When using manual clock switchover, the difference between inclk0 and inclk1 can be more than 100% (2×). However, differences in frequency, phase, or both, of the two clock sources may cause the I/O PLL to lose lock. Resetting the I/O PLL ensures that you maintain the correct phase relationships between the input and output clocks.
  • Both inclk0 and inclk1 must be running when the extswitch signal goes low to initiate the manual clock switchover event. Failing to meet this requirement causes the clock switchover to not function properly.
  • After a switchover occurs, there may be a finite resynchronization period for the I/O PLL to lock onto a new clock. The time it takes for the I/O PLL to relock depends on the I/O PLL configuration.
  • If the phase relationship between the input clock to the I/O PLL and the output clock from the I/O PLL is important in your design, assert the reset signal for at least 10 ns after performing a clock switchover. Wait for the locked signal to go high and be stable before re-enabling the output clocks from the I/O PLL.
  • The VCO frequency gradually decreases when the current clock is lost and then increases as the VCO locks on to the backup clock, as shown in the following figure.
Figure 24. VCO Switchover Operating Frequency