Agilex™ 7 Clocking and PLL User Guide: M-Series

ID 769001
Date 4/01/2024
Document Table of Contents

2.2.10. PLL Cascading

M-Series devices support PLL-to-PLL cascading. You can cascade a maximum of two PLLs. PLL cascading synthesizes more output clock frequencies than a single PLL.

M-Series devices support the following PLL-to-PLL cascading modes for I/O bank I/O PLL and I/O Bank Fabric-Feeding I/O PLL. UIB fabric-feeding I/O PLL do not support cascading.
  • I/O Bank I/O-PLL-to-I/O Bank I/O-PLL cascading
  • I/O Bank I/O-PLL-to-I/O Bank fabric-feeding I/O-PLL cascading
  • I/O Bank fabric-feeding I/O-PLL-to I/O Bank I/O-PLL cascading
Cascading of PLLs can be done via two paths: via dedicated cascade path or via core clock fabric.
  • Cascading via dedicated cascade path—upstream I/O PLL and downstream I/O PLL must be in the same I/O column and are placed adjacently.
  • Cascading via core clock fabric—no restriction on locations of upstream and downstream I/O PLL.

The permit_cal input of the downstream I/O PLL must be connected to the locked output of the upstream I/O PLL in both PLL cascading modes.

The following figures show the connectivity required between the upstream and downstream I/O PLL for both the PLL cascading modes.

Figure 17. Cascading Via Dedicated Cascade Path
Figure 18. Cascading Via Core Clock Fabric