Agilex™ 7 Clocking and PLL User Guide: M-Series

ID 769001
Date 4/01/2024
Document Table of Contents

3.7. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP

To achieve 5% duty cycle for fOUT_EXT ≥ 300 MHz, you can only use tx_outclk port from the LVDS SERDES Intel® FPGA IP. Refer to the following guidelines for the settings in the LVDS SERDES Intel® FPGA IP:

  1. In the General Setting tab, select TX as functional mode. For data rate, enter a value 2× of your desired frequency. As an example, if your desired frequency is 500 MHz, enter 1000 as data rate.
  2. In the PLL settings tab, set your desired input frequency.
  3. In the Transmitter Settings tab, enable tx_outclock port and select 2 as Tx_outclock division factor.