Intel® FPGA AI Suite: Getting Started Guide

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ID 768970
Date 4/05/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite Getting Started Guide 2. About the Intel® FPGA AI Suite 3. Installing the Intel® FPGA AI Suite 4. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites 5. Installing the Intel FPGA AI Suite Compiler and IP Generation Tools 6. Intel® FPGA AI Suite Quick Start Tutorial A. Installation Notes for Other Operating Systems B. Intel® FPGA AI Suite Getting Started Guide Archives C. Intel® FPGA AI Suite Getting Started Guide Document Revision History
3. Installing the Intel® FPGA AI Suite x
3.1. Intel® FPGA AI Suite Directory Structure
4. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites x
4.1. PCIe-based Design Example Hardware Prerequisites 4.2. PCIe-based Design Example Operating System Prerequisites 4.3. PCIe-based Design Example Software Prerequisites
4.3. PCIe-based Design Example Software Prerequisites x
4.3.1. Additional Software Prerequisites for the PCIe-based Design Example for Intel Agilex® 7 Devices 4.3.2. Additional Software Prerequisites for the PCIe-Based Design Example for Intel® Arria® 10 Devices
5. Installing the Intel FPGA AI Suite Compiler and IP Generation Tools x
5.1. Supported FPGA Families 5.2. Operating System Prerequisites 5.3. Software Prerequisites 5.4. Installing the Intel® FPGA AI Suite Using System Package Management Tools 5.5. Installing the Intel® FPGA AI Suite Into an Alternative Location
5.3. Software Prerequisites x
5.3.1. OpenVINO™ Toolkit 5.3.2. Intel® Quartus® Prime Pro Edition Software
6. Intel® FPGA AI Suite Quick Start Tutorial x
6.1. Creating a Working Directory 6.2. Preparing OpenVINO™ Model Zoo and Model Optimizer 6.3. Preparing a Model 6.4. Running the Graph Compiler 6.5. Preparing an Image Set 6.6. Programming the FPGA Device 6.7. Performing Inference on the PCIe-Based Example Design 6.8. Building an FPGA Bitstream for the PCIe Example Design 6.9. Building the Example FPGA Bitstreams 6.10. Preparing a ResNet50 v1 Model 6.11. Performing Inference on the Inflated 3D (I3D) Graph 6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics
6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics x
6.12.1. Preparing a YOLOv3 Model 6.12.2. Preparing a COCO Validation Dataset and Annotations 6.12.3. Inference on YOLOv3 and Calculating Accuracy Scores
A. Installation Notes for Other Operating Systems x
A.1. CentOS* 7 Installation Notes
1. Intel® FPGA AI Suite Getting Started Guide
2. About the Intel® FPGA AI Suite
3. Installing the Intel® FPGA AI Suite
4. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites
5. Installing the Intel FPGA AI Suite Compiler and IP Generation Tools
6. Intel® FPGA AI Suite Quick Start Tutorial
A. Installation Notes for Other Operating Systems
B. Intel® FPGA AI Suite Getting Started Guide Archives
C. Intel® FPGA AI Suite Getting Started Guide Document Revision History

C. Intel® FPGA AI Suite Getting Started Guide Document Revision History

Document Version Intel® FPGA AI SuiteVersion Changes
2023.04.05 2023.1
  • Added "Performing Inference on the i3d Graph".
  • Renamed thedlac command. The Intel® FPGA AI Suite compiler command is now dla_compiler.
  • Updated the Intel® Agilex™ product family name to "Intel Agilex® 7."
2022.12.23 2022.2
  • Update for the Debian package-based install.
  • Add walk-through for validating a YOLOv3 model.
  • Update to account for the new Terasic DE10-Agilex BSP ZIP file.
  • Renamed dla_create_and_build_pcie_ed.py to dla_build_example_design.py

2022.04.27

2022.1
  • Minor fixes to some file names, including one for the running inference in the AOT flow on the FPGA.

2022.04.12

2022.1
  • Notes on installing CMake for CentOS 7.
  • Clarifications to the Model Zoo and Model Optimizer install instructions.

2022.04.08

2022.1
  • Extensively revised installation instructions.
  • Added installation information for the PCI-based design examples.
  • Enhanced details for Intel Agilex devices.
  • Added a quick-start tutorial.
  • Removed supplementary performance details.

2021.09.10

2021.2
  • Added information for initial Intel Agilex device family support.

2021.04.30

2021.1
  • Expanded list of tasks performed by the Intel FPGA AI Suite Compiler.
  • Distinguished more clearly between requirements for the IP and requirements for the Example Designs.

2020.12.04

2020.2
  • Renamed the script that sets the Intel FPGA AI Suite environment variables to init_env.sh. It was called coredla_developer_init_env.sh in earlier releases.

2020.10.30

2020.1
  • Initial release.
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