MACsec Intel® FPGA System Design User Guide

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ID 767516
Date 3/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Architecture 3. Interface Overview 4. Parameters 5. Configuration Registers 6. Software Architecture 7. Generating the System Design 8. Document Revision History for MACsec System Design User Guide A. Release Notes
1. Introduction x
1.1. Terminology 1.2. Release Information 1.3. System Requirements
2. Architecture x
2.1. System Architecture 2.2. Data Path Between Ethernet MAC and MACsec 2.3. Data Path Between MACsec and MCDMA 2.4. Data Path Between MACsec and Packet Generator/Checker (Packet Client) 2.5. Data Path Illustrations 2.6. Interrupts 2.7. Packet FIFO 2.8. AXI-ST Rate Controller 2.9. Error Handling 2.10. Top Level Signals
2.2. Data Path Between Ethernet MAC and MACsec x
2.2.1. Ethernet Subsystem
2.2.1. Ethernet Subsystem x
2.2.1.1. Data Receiving from MACsec to E/F-Tile Hard IP 2.2.1.2. Data Transmitting from E/F-tile Hard IP to MACsec 2.2.1.3. Order of Ethernet Transmission 2.2.1.4. E/F-Tile Hard IP Reset Sequence
2.3. Data Path Between MACsec and MCDMA x
2.3.1. AXI-ST Multi-Segment to Single-Segment Conversion 2.3.2. MCDMA
2.4. Data Path Between MACsec and Packet Generator/Checker (Packet Client) x
2.4.1. Packet Client 2.4.2. Packet Generation and Check
2.5. Data Path Illustrations x
2.5.1. MACsec Interface Signal Names
2.6. Interrupts x
2.6.1. MCDMA MSI-X Table Configuration
3. Interface Overview x
3.1. Clocking 3.2. Resets
5. Configuration Registers x
5.1. System Register Map
5.1. System Register Map x
5.1.1. Packet Client Register Map 5.1.2. Interrupt Controller Register Map
6. Software Architecture x
6.1. MACsec Key Agreement Protocol 6.2. Driver Functional Requirements 6.3. Software Requirements 6.4. Software Overview 6.5. MACsec IP APIs Sequence 6.6. Functions 6.7. Software Tools
6.4. Software Overview x
6.4.1. McDMA Driver Kernel Module 6.4.2. MACsec IP APIs 6.4.3. Linux MACsec Driver Kernel Module 6.4.4. IP Tool 6.4.5. WPA Supplicant
6.4.2. MACsec IP APIs x
6.4.2.1. SDK
6.5. MACsec IP APIs Sequence x
6.5.1. MACsec Initialization Sequence
6.5.1. MACsec Initialization Sequence x
6.5.1.1. MACsec Reset Sequence 6.5.1.2. TX Configuration Sequence 6.5.1.3. RX Configuration Sequence 6.5.1.4. TX Rekeying Sequence 6.5.1.5. RX Rekeying Sequence 6.5.1.6. Cut Through/Store Forward Mode 6.5.1.7. User Single/Multi Port Settings 6.5.1.8. Encrypt/Decrypt Port 6.5.1.9. Port Priority 6.5.1.10. Interrupt Generation and Register
6.5.1.1. MACsec Reset Sequence x
6.5.1.1.1. GLOBAL Reset 6.5.1.1.2. PORT Reset 6.5.1.1.3. Secure Association (SA) Reset
6.6. Functions x
6.6.1. macsec_initilize 6.6.2. macsec_get_attributes 6.6.3. macsec_get_sa_attributes 6.6.4. macsec_set_attributes 6.6.5. macsec_set_sa_attributes 6.6.6. macsec_read_register 6.6.7. macsec_write_register 6.6.8. macsec_set_port_configuration 6.6.9. macsec_rate_configuration 6.6.10. macsec_single_or_multi_port 6.6.11. macsec_crypto_mode 6.6.12. macsec_port_priority 6.6.13. macsec_register_isr
6.7. Software Tools x
6.7.1. IP Tool 6.7.2. WPA_Supplicant 6.7.3. CLI Debug Tool
6.7.3. CLI Debug Tool x
6.7.3.1. Functional Requirements 6.7.3.2. Features Overview 6.7.3.3. Design with HOST 6.7.3.4. Netlink Interface 6.7.3.5. SDK 6.7.3.6. Design Overview
7. Generating the System Design x
7.1. Software Requirements 7.2. Obtaining the Reference Design 7.3. Reference Design Directory Structure 7.4. Simulation Command Arguments 7.5. Simulation Test Cases 7.6. Complete Simulation Command 7.7. Simulation Requirements 7.8. Running Non-UVM Simulation 7.9. Running UVM Simulation 7.10. Building, Installing, and Running the Software 7.11. Building the Hardware Design
7.4. Simulation Command Arguments x
7.4.1. Simulation -d Options
1. Introduction
2. Architecture
3. Interface Overview
4. Parameters
5. Configuration Registers
6. Software Architecture
7. Generating the System Design
8. Document Revision History for MACsec System Design User Guide
A. Release Notes

5.1.1. Packet Client Register Map

The table below describes the packet client CSRs.
Table 9.  Packet Client Register Map
Offset Name Bit Type HW Reset Value Description
0x000 CFG_PKT_CL_CTRL [31:20] RO 23’b0 Reserved.
[19:12] RW 8’b0

Number of Idle cycles to be inserted between packets.

Applicable in dynamic mode when CFG_PKT_CL_CTRL[9] is set to 1.

[11:10] RW 2’b00

00: Reserved (Random).

01: Fixed length mode.

10: Incremental length mode.

11: Reserved.

Only applicable in dynamic packet gen mode.

[9] RW 1’b0

0: For transmission with random gap in between packets. Only applicable in Dynamic packet gen mode.

1: For transmission with fixed gap in between packets.

[8] RW 1’b0 When set to ‘1’, it clears Internal Tx & Rx Status counters. Once set to ‘1’, CPU must clear this bit afterwards.
[7] RW 1’b0 When set to ‘1’, it clears Tx & Rx Status counter CSRs. Once set to ‘1’, CPU must clear this bit afterwards.
[6] RW 1’b0 When set to ‘1’, it takes snapshot of Internal Tx & Rx Status counters to CSRs. Once set to ‘1’, CPU must clear this bit.
[5] RW 1’b0

0: Disable Packet checker

.

1: Enable Packet checker.

Checker block generates reference data based on its own packet generator setting.

[4] RW 1’b0

0: Reserved.

1: Select dynamic mode packet generation.

[3] RW 1’b0

0: Deassert checker/packetgen soft reset.

1: Assert checker/packetgen soft reset

CSR block is not reset by this soft reset. Use this to soft reset blocks after a sequence execution.
[2] RW 1’b0

0: Generates traffic in one shot mode.

1: Reserved.
[1] RO 1’b0

Reserved.

[0] RW 1’b0

1: Tx Traffic is enabled from packet client.

0: Tx traffic is disabled from packet client.

0x004

RESERVED

 [31:16]      
[15:0]      
0x008

RESERVED

 [31:16]      
[15:0]      
0x00C DYN_DMAC_ADDR_U [31:16] RO 0x0 Reserved.
[15:0] RW 0x1234

Destination MAC address (upper 16 bits).

Only applicable in dynamic packet mode.

0x010 DYN_DMAC_ADDDR_L [31:0] RW

0x56780A

DD

Destination MAC address (lower 32 bits).

Only applicable in dynamic packet gen mode.

0x014 DYN_SMAC_ADDR_U [31:16] RO 0x0 Reserved.
[15:0] RW 0x8765

Source MAC address (upper 16 bits).

Only applicable in dynamic packet gen mode.

0x018 DYN_SMAC_ADDR_L [31:0] RW

0x0x4321

0ADD

Source MAC address (lower 32 bits).

Only applicable in dynamic packet mode.

0x01C DYN_PKT_NUM [31:0] RW 0xA

Specifies the number of packets to transmit from the packet generator.

Only applicable in dynamic packet gen mode.

0x020 DYN_PKT_SIZE_CFG [31:30] RO 0x0  
[29:16] RW 0x2580

Specifies the transmit packet size in bytes.

Specifies the upper limit of the packet size in bytes. This is only applicable to incremental mode within dynamic gen packet mode.

[15:14] RO 0x0 Reserved.
[13:0] RW 0x0040

Specifies the transmit packet size in bytes.

For fixed mode, these bits specify the transmit packet size in bytes.

For incremental mode, these bits specify the incremental bytes for a packet.

Only applicable in dynamic packet gen mode.

0x024 STAT_TX_SOP_CNT_L [31:0] RO 32’b0

TX Start of packet counter lower 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’.

0x028 STAT_TX_SOP_CNT_U [31:0] RO 32’b0

TX Start of packet counter upper 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’.

0x02C STAT_TX_SOP_CNT_L [31:0] RO 32’b0

TX End of packet counter lower 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’.

0x030 STAT_TX_SOP_CNT_U [31:0] RO 32’b0 TX End of packet counter upper 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’.
0x034 STAT_TX_ERR_CNT_L [31:0] RO 32’b0

TX Error counter lower 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’.

0x038 STAT_TX_ERR_CNT_U [31:0] RO 32’b0

TX Error counter upper 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’.

0x03C STAT_RX_SOP_CNT_L [31:0] RO 32’b0

RX Start of packet counter lower 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’.

0x040 STAT_RX_SOP_CNT_U [31:0] RO 32’b0

RX Start of packet counter upper 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’.

0x044 STAT_RX_EOP_CNT_L [31:0] RO 32’b0 RX End of packet counter lower 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’.
0x048 STAT_RX_EOP_CNT_U [31:0] RO 32’b0

RX End of packet counter upper 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’.

0x04C STAT_RX_ERR_CNT_L [31:0] RO 32’b0

RX Error counter lower 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’.

0x050 STAT_RX_ERR_CNT_U [31:0] RO 32’b0

RX Error counter upper 32bits CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’.

0x054 STAT_SYSTEM_MISC [31:5] RO 31’b0 Reserved.
[4] RO 1’b0

0: HSSI SS rx_pcs_ready is not asserted.

1: HSSI SS rx_pcs_ready is asserted.

[3] RO 1’b0

0: HSSI SS tx_pll_locked is not asserted.

1: HSSI SS tx_pll_locked is asserted.

[2] RO 1’b0

0: HSSI SS tx_lanes_stable is not asserted.

1: HSSI SS tx_lanes_stable is asserted.

[1] RO 1’b0

0: System Reset Sequence is not complete.

1: System Reset Sequence is complete.

[0] RO 1’b0

0: SADB Configuration is not complete.

1: SADB Configuration is complete.

0x058 STAT_CHECKER_MISC [31:1] RO 28’b0 Reserved.
[1] RO 1’b0 Reserved.
[0] RO 1’b0

1: Data mismatches at data checker.

0: Data does not mismatch.

0x05C STAT_CHECKER_CNT [31:1] RO 32’b0

Live Packet count received at the checker.

0x060 PKTCLI_RX_BYTE_CNT_L [31:0] RO 32’h0

Lower bits for counter to count number of bytes received.

0x064 PKTCLI_RX_BYTE_CNT_U [31:0] RO 32’h0

Upper bits for counter to count number of bytes received.

0x068 PKTCLI_TX_BYTE_CNT_L [31:0] RO 32’h0

Lower bits for counter to count number of bytes sent.

0x06C PKTCLI_TX_BYTE_CNT_U [31:0] RO 32’h0

Upper bits for counter to count number of bytes sent.

0x070 PKTCLI_TX_NUM_TICKS_L [31:0] RO 32’h0

Number of clock cycles for all the packets to be sent. (lower bits).

0x074 PKTCLI_TX_NUM_TICKS_U [31:0] RO 32’h0

Number of clock cycles for all the packets to be sent. (upper bits).

0x078 PKTCLI_RX_NUM_TICKS_L [31:0] RO 32’h0

Number of clock cycles for all the packets to be received. (lower bits).

0x07C PKTCLI_RX_NUM_TICKS_U [31:0] RO 32’h0

Number of clock cycles for all the packets to be received. (upper bits).

Level Two Title