MACsec Intel® FPGA System Design User Guide

ID 767516
Date 3/31/2024
Document Table of Contents

2.6. Interrupts

The MCMDA interface supports 4 MSI-X interrupts per channel for one user interrupt per queue in each direction. If your logic needs to support multiple interrupts, then you should implement local logic which retains the interrupt requests from different sources and waits for their turn to request an interrupt to the MCDMA which in turn generates the MSI-X. A SW routine to read the interrupt source can then take further action.

Each DMA channel is allocated 4 MSI-X vectors:
  • 2’b00: H2D DMA Vector
  • 2’b01: H2D Event Interrupt
  • 2’b10: D2H DMA Vector
  • 2’b11: D2H Event Interrupt

You may use H2D event interrupt or D2H event interrupt to signal pre-defined events. In the interrupt vector table, these 4 vector entries are available per channel. The SW is expected to configure the entries if it is expecting an interrupt from your logic.

An interrupt controller as shown in the figure below is implemented. Currently there are only two MACsec interrupts as irq sources (one per channel) and only one is outstanding at any given time.
Figure 24. Interrupt Controller

Each channel’s interrupt controller may support up to N number of IRQ signals from different modules. The usr_event_msix_data_i that goes to MCDMA indicates the IRQ from which channel only. The SW Interrupt routine’s responsibility is to probe the register space of each interrupt controller to know which input IRQ caused the channel specific interrupt. Based on this the SW can go and read the interrupt status register of the IP module that asserted the IRQ. The two-step process from the SW is mentioned above. The SW application can clear any particular interrupt bit in the interrupt controller after servicing it and can then service the next one if it is asserted again.