MACsec Intel® FPGA System Design User Guide

ID 767516
Date 3/31/2024
Document Table of Contents

3.1. Clocking

This design uses multiple clock domains as the Ethernet MAC (25G/100G) works at a different rate compared to the PCIe+MCDMA (128G) and the MACsec (200G). The interface clocks are shown below.
Table 6.  Clocking Interfaces
User Interface Clock Frequency (MHz) Remarks
HSSI-SS AXI-ST Interface 402.832 Fixed for 25G/100G configuration
HSSI-SS AXI-Lite Interface 100 CSR clock. Use a bridge for MCDMA app_clk to 100
MACSec AXI-ST interface 400 As per MACSec HAS requirement (throughput of 200G)
MACSec AXI-Lite Interface 100 CSR clock
Crypto AXI-ST Interface 400 As per Crypto solution HAS for inline processing
MCDMA AVST Interface 250/500 For Gen3x16/Gen4x16 configuration respectively
Packet Generator/Checker 400 MACSec interface clock
Figure 28. Clocking Structure
Table 7.  Reference Clock Frequencies
Reference Clocks Clock Frequency (MHz) Remarks
HSSI-SS or E/F-Tile 156.25 External source
PCIe 100 External source
IOPLL 100 External source. Generate MACSec, Crypto and CSR clock sources