MACsec Intel® FPGA System Design User Guide

ID 767516
Date 3/31/2024
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Document Table of Contents

5.1.2. Interrupt Controller Register Map

The table below describes the interrupt controller register map.
Table 10.  Interrupt Controller Register Map
Offset Name Bit Type HW Reset Value Description
0x000 INTC_CSR_STATUS [31:1] RO

00

Reserved.
[0] RO

00

To check the status of the interrupt.

After every interrupt is serviced the status register must be cleared.
0x004 INTC_CSR_ENABLE [31:1] RO

00

Reserved.
[0] RW

00

For every interrupt asserted the enable should be asserted for the valid msix_data to be sent to MCDMA.
0x08 INTC_CSR_CLEAR [31:1] RO

00

Reserved.
[0] WC

00

A clear pulse can be generated by writing into this register which clears the status.