AN 988: Using the Board-Aware Flow: in the Intel® Quartus® Prime Pro Edition Software

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ID 757339
Date 1/09/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Using the Board-Aware Flow in the Intel® Quartus® Prime Pro Edition Software
2. Using the Board-Aware Flow in the Intel® Quartus® Prime Pro Edition Software x
2.1. Document Prerequisites 2.2. Downloading and Extracting Supporting Files 2.3. Accessing Intel FPGA Design Examples 2.4. Using the Board-Aware Flow in Platform Designer 2.5. Document Revision History of AN 988: Using the Board-Aware Flow in the Intel® Quartus® Prime Pro Edition Software
2.3. Accessing Intel FPGA Design Examples x
2.3.1. Accessing Pre-Installed Design Examples 2.3.2. Accessing Downloaded Design Examples 2.3.3. Accessing Online Design Examples
2.4. Using the Board-Aware Flow in Platform Designer x
2.4.1. Step 1: Specify a Target Board for the Project 2.4.2. Step 2: Create a New Board File 2.4.3. Step 3: Create IP Presets for the Board 2.4.4. Step 4: Create a Design Using Board and Preset Files 2.4.5. Step 5: Compile and Verify the Design 2.4.6. Step 6: Configure the Board with Software
1. Answers to Top FAQs
2. Using the Board-Aware Flow in the Intel® Quartus® Prime Pro Edition Software

2.4. Using the Board-Aware Flow in Platform Designer

The board-aware flow is fully integrated within the Platform Designer GUI to simplify and accelerate the process of appropriately configuring IP and systems for a target board.

Platform Designer allows you to create a system that targets a specific development board, rather than only targeting a specific FPGA device. When you target a specific development board, Platform Designer is aware of the target board (board-aware) which simplifies the IP parameterization, pin assignments, and export of interfaces for the system.

The board-aware flow uses IP presets together with a board definition file that specifies the details of a target board. You can use (and reuse) the board definition and IP presets to automatically include the appropriate IP pin assignments, parameters, and exported interfaces for the target development board during system generation.

The following example board-aware flow example creates an LED system based on the PIO Intel® FPGA IP design example:

Figure 8. PIO IP-Based LED Design Block Diagram



Section Content
Step 1: Specify a Target Board for the Project
Step 2: Create a New Board File
Step 3: Create IP Presets for the Board
Step 4: Create a Design Using Board and Preset Files
Step 5: Compile and Verify the Design
Step 6: Configure the Board with Software

Level Two Title