AN 988: Using the Board-Aware Flow: in the Intel® Quartus® Prime Pro Edition Software

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ID 757339
Date 1/09/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Using the Board-Aware Flow in the Intel® Quartus® Prime Pro Edition Software
2. Using the Board-Aware Flow in the Intel® Quartus® Prime Pro Edition Software x
2.1. Document Prerequisites 2.2. Downloading and Extracting Supporting Files 2.3. Accessing Intel FPGA Design Examples 2.4. Using the Board-Aware Flow in Platform Designer 2.5. Document Revision History of AN 988: Using the Board-Aware Flow in the Intel® Quartus® Prime Pro Edition Software
2.3. Accessing Intel FPGA Design Examples x
2.3.1. Accessing Pre-Installed Design Examples 2.3.2. Accessing Downloaded Design Examples 2.3.3. Accessing Online Design Examples
2.4. Using the Board-Aware Flow in Platform Designer x
2.4.1. Step 1: Specify a Target Board for the Project 2.4.2. Step 2: Create a New Board File 2.4.3. Step 3: Create IP Presets for the Board 2.4.4. Step 4: Create a Design Using Board and Preset Files 2.4.5. Step 5: Compile and Verify the Design 2.4.6. Step 6: Configure the Board with Software
1. Answers to Top FAQs
2. Using the Board-Aware Flow in the Intel® Quartus® Prime Pro Edition Software

2.4.5. Step 5: Compile and Verify the Design

Follow these steps to compile the top-level design that includes the pio_led Platform Designer system.
  1. After Platform Designer HDL generation is complete, click Processing > Start Compilation. The Compiler runs for approximately 15 minutes, depending on your system, and generates the SOF programming file following successful compilation.
  2. When full compilation is complete, click Assignments > Pin Planner to verify the following appropriate pin assignments are implemented during compilation:
    Figure 22. Verifying Location Assignments in Pin Planner


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