AN 988: Using the Board-Aware Flow: in the Intel® Quartus® Prime Pro Edition Software

Download PDF
ID 757339
Date 1/09/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Using the Board-Aware Flow in the Intel® Quartus® Prime Pro Edition Software
2. Using the Board-Aware Flow in the Intel® Quartus® Prime Pro Edition Software x
2.1. Document Prerequisites 2.2. Downloading and Extracting Supporting Files 2.3. Accessing Intel FPGA Design Examples 2.4. Using the Board-Aware Flow in Platform Designer 2.5. Document Revision History of AN 988: Using the Board-Aware Flow in the Intel® Quartus® Prime Pro Edition Software
2.3. Accessing Intel FPGA Design Examples x
2.3.1. Accessing Pre-Installed Design Examples 2.3.2. Accessing Downloaded Design Examples 2.3.3. Accessing Online Design Examples
2.4. Using the Board-Aware Flow in Platform Designer x
2.4.1. Step 1: Specify a Target Board for the Project 2.4.2. Step 2: Create a New Board File 2.4.3. Step 3: Create IP Presets for the Board 2.4.4. Step 4: Create a Design Using Board and Preset Files 2.4.5. Step 5: Compile and Verify the Design 2.4.6. Step 6: Configure the Board with Software
1. Answers to Top FAQs
2. Using the Board-Aware Flow in the Intel® Quartus® Prime Pro Edition Software

2.2. Downloading and Extracting Supporting Files

  1. Download and extract the Board-Aware Design Example Supporting Files to a directory on your computer. Do not use spaces in the directory path name.
  2. View the extracted tutorial design files and directory structure. board_aware_example_agilex.zip contains the following files:
Table 1.  Supporting Design Example Files
File Description
pin_pio.tcl Tcl pin constraints file that contains appropriate pin assignments for the system. You can optionally load this file rather than manual entry.
pio_led.out.sdc Synopsys Design Constraints file that contains appropriate timing constraints for the completed design.
issp.ip Represents the In-System Sources and Probes Intel® FPGA IP in the design for use in debugging the design.
resetrelease.ip Represents the Reset Release Intel FPGA IP in the design. This IP outputs nINIT_DONE after finishing device initialization. User mode initialization can begin as soon as the nINIT_DONE signal asserts.
Level Two Title