MACsec Intel® FPGA IP User Guide

ID 736108
Date 12/19/2022

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6.4.2. Packet Framer

The plaintext packet entering the Encryption Framer logic block is framed with the SecTAG and IV. One example is shown below, where 8 packets from port/stream 0 are accessing 4 different Crypto channels. Cycle 0 to 11 are showing the Crypto channel allocation cycles where a key is sent to the Crypto HIP. From cycle 11, 2 packets data payloads are packed in the same cycle to improve performance. Crypto HIP supports this packet packing format when the 2 assumptions below are met:
  • No channel allocation (key) is sent into the Crypto HIP.
  • The start of packet (IV, AAD_LEN) can only happen on the 16 bytes align segment. For example, cycle 12 shows one 8B idle segment is inserted to ensure the next start of packet happens on the 4th segment instead of the 3rd segment.
Figure 30. 8 Packets Accessing 4 Crypto ChannelsIn this table, each colored block represents a different cryptographic channel.