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1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. MACsec Intel® FPGA IP Example Design
6. Functional Description
7. Configuration Registers for MACsec IP
8. MACsec Intel FPGA IP User Guide Archives
9. Document Revision History for the MACsec Intel FPGA IP User Guide
2.2.1.1. Common Port Mux Interface
2.2.1.2. Common Port Demux Interface
2.2.1.3. Controlled Port Mux Interface
2.2.1.4. Controlled Port Demux Interface
2.2.1.5. Uncontrolled Port RX Interface
2.2.1.6. Uncontrolled Port TX Interface
2.2.1.7. Crypto RX Interface
2.2.1.8. Crypto TX Interface
2.2.1.9. Management Interface
2.2.1.10. Decrypt Port Mux Management Interface
2.2.1.11. Decrypt Port Demux Management Interface
2.2.1.12. Encrypt Port Mux Management Interface
2.2.1.13. Encrypt Port Demux Management Interface
2.2.1.14. Crypto IP Management Bus
2.2.2.1. Common Port Mux Interface Waveform
2.2.2.2. Common Port Demux Interface Waveform
2.2.2.3. Controlled Port Mux Interface Waveform
2.2.2.4. Controlled Port Demux Interface Waveform
2.2.2.5. Uncontrolled Port RX Interface Waveform
2.2.2.6. Uncontrolled Port TX Interface Waveform
2.2.2.7. Crypto RX Waveform
2.2.2.8. Crypto TX Waveform
2.2.2.9. MACsec Management Interface (Read)
2.2.2.10. MACsec Management Interface (Write)
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2.1. Block Diagram
Figure 3. MACsec IP Block Diagram