MACsec Intel® FPGA IP User Guide

ID 736108
Date 12/19/2022

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Document Table of Contents Crypto RX Interface

This interface is only exposed when CRYPTO_QHIP_EN = 0. Setting CRYPTO_QHIP_EN to '0' is not recommended.

Note: For more information on how to use this interface, refer to Symmetric Cryptographic Intel FPGA Hard IP User Guide.
Table 13.  Crypto RX Interface
Signal Name Width Direction Description
app_ip_st_clk 1 In Clock
app_ip_st_areset_n 1 In Asynchronous reset
aes_app_ip_rx_tvalid 1 In Valid
aes_ip_app_rx_tready 1 Out Ready
aes_ip_app_rx_tid 32 In

Transaction Stream/Channel ID


Stream and Channel ID for Packet 0 (Both Single Packet Mode and Multi Packet Mode) and Packet 1 (Multi Packet Mode only).

  • TID[31:26] – Stream ID for packet 1
  • TID[25:16] – Channel ID for packet 1
  • TID[15:10] – Stream ID for packet 0
  • TID[9:0] – Channel ID for packet 0

Valid on every transfer of the packet

aes_app_ip_rx_tdata 512 In Data
aes_app_ip_rx_tkeep 64 In

1'b1 for data byte, 1'b0 for null byte.

Note: This signal does not allow a null byte in the beginning or middle of the transfer. It is only applicable during the end of the transfer.
aes_app_ip_rx_tlast 1 In Last, indicates end of transfer.
aes_app_ip_rx_tuser.algorithm_types 1 In

Indicates AES or SM4 mode for the current clock cycle

  • 1: SM4;
  • 0: AES
aes_app_ip_rx_tuser.encrypt_decrypt 1 In

Indicates Encrypt or Decrypt mode for the current clock cycle

  • 1: decrypt;
  • 0: encrypt
aes_app_ip_rx_tuser.key_128b_256b 1 In

Indicates 128 bit key size or 256 bit key size mode for the current clock cycle

  • 0: 128 bit key size;
  • 1: 256 bit key size
aes_app_ip_rx_tuser.pattern 4 In

This is a 4-bit encoding for the Traffic Pattern types.

4'b 0010: MACsec

aes_app_ip_rx_tuser.mac_iv_tweak_en 1 In Indicates the data fields carry an IV (or tweak for XTS) and at the output this field indicates the data contains the MAC.
aes_app_ip_rx_tuser.data_en 1 In Indicates that for a given pattern ID the data bits carry the raw data into the crypto cores
aes_app_ip_rx_tuser.next_packet_en 1 In Indicates that there is a start of a new packet midway through the data lines. This is only a valid signal when there is a tlast signal asserted in the same clock and the tkeep.
aes_app_ip_rx_tuser.error_status 1 In Output signal to the fabric indicating any error on the inputs. 0 means there is no error.
aes_app_ip_rx_tuser.error_code 5 In Output signal indicating to the fabric the error code for this cycle.
aes_app_ip_rx_tuser.auth_error 1 In Indicates whether there is any integrity check error during packet decryption. Valid when tlast is asserted.
aes_app_ip_rx_tuser.internal_error 1 In Indication from the QHIP of an internal error detection. This signal is synchronous and when asserted requires the user to read the error status code and CSR’s to detect the error. It also requires the user to drive in the TUser bit for error_clear with the right profile, stream and channel ID of the error in order to use the QHIP again on that profile and channel.
aes_app_ip_rx_tuser_last_segment<segment number> 1 In

Packet segmentation boundary indication for higher bandwidth transfer.

  • aes_app_ip_rx_tuser_last_segment0

  • aes_app_ip_rx_tuser_last_segment1

  • aes_app_ip_rx_tuser_last_segment2

  • aes_app_ip_rx_tuser_last_segment3