MACsec Intel® FPGA IP User Guide

ID 736108
Date 12/19/2022

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5. MACsec Intel® FPGA IP Example Design

The block diagram below shows the MACsec IP design example.
Figure 19. MACsec IP Design Example

The IP GUI can generate (5) individual design examples. In order to generate one of the variants below, please select the following options for your project and IP parameter settings.

Table 30.  Available MACsec Design Example Variant
Design E-tile Device F-tile Device Number of TX Ports Number of TX + RX Ports Port Data Width Maximum Crypto Channels
1x25G AGFC023R25A2I2V AGID019R18A2E2V 1 2 64 16
2x25G AGFC023R25A2I2V AGID019R18A2E2V 2 4 64 32
4x25G AGIC035R39A1E2V 4 8 64 64
1x100G AGIC035R39A1E2V 1 2 256 16
1x200G TX Simplex AGIC035R39A1E2V 1 1 512 8
Follow the steps below to run the design example in simulation:
  1. Create a project using one of the above devices.
  2. Create a MACsec IP variant using the above parameters for the device you have selected.
  3. Click the Generate Example Design button. The Select Example Design Directory appears.
  4. Select the directory where you want the Example Design to be placed.
  5. Click OK. Your design example is now generated in your chosen directory.
  6. Navigate to the <Example Design Directory>/example_testbench/.
  7. Execute a proper command to kick off simulation in your supported simulator.
Note: The MACsec Design Example incorporates the Crypto ICA Hard IP. You can integrate your own soft Crypto IP by setting CRYPTO_QHIP_EN to '0', which exposes the Crypto interfaces as shown in Crypto RX Interface and Crypto TX Interface. This configuration has not yet been validated or verified.
The table below shows the steps to simulate the testbench.
Table 31.  Steps to Simulate the Testbench
Simulator Instructions
Synopsys* VCS*

In the command line, type:


Synopsys VCS MX

In the command line, type:


Use this script when the design contains Verilog HDL and System Verilog with VHDL.

QuestaSim* or Questa* Intel FPGA Edition

In the command line, type:

vsim -do

If you prefer to simulate without bringing up the GUI, type:

vsim -c -do

The figure below shows a sample output of the simulation.
Figure 20. Simulation Output