F-Tile JESD204B Intel® FPGA IP User Guide

ID 723907
Date 4/23/2024
Document Table of Contents

1. F-Tile JESD204B IP Quick Reference

Updated for:
Intel® Quartus® Prime Design Suite 24.1
IP Version 2.2.0

The F-Tile JESD204B Intel® FPGA IP is a high-speed point-to-point serial interface intellectual property (IP).

Note: For system requirements and installation instructions, refer to Intel® FPGA Software Installation & Licensing.
Table 1.  Brief Information About the F-Tile JESD204B IP



Protocol Features

  • Joint Electron Device Engineering Council (JEDEC) JESD204B.01, 2012 standard release specification
  • Device subclass:
    • Subclass 0—Backwards compatible to JESD204A.
    • Subclass 1—Uses SYSREF signal to support deterministic latency.
    • Subclass 2—Uses SYNC_N detection to support deterministic latency.

Core Features

  • Data rate of up to 12.5 gigabits per second (Gbps)—per JESD204B specification
  • Data rate of up to 20 Gbps—not certified per JESD204B specification (uncharacterized support)
  • Single or multiple lanes (up to 8 lanes per link)
  • Serial lane alignment and monitoring
  • Lane synchronization
  • Modular design that supports multidevice synchronization
  • MAC and PHY partitioning
  • Deterministic latency support
  • 8B/10B encoding
  • Scrambling/Descrambling
  • Avalon® streaming interface for transmit and receive datapaths
  • Avalon® memory-mapped interface for Configuration and Status registers (CSR)
  • Dynamic generation of simulation testbench

Typical Application

  • Wireless communication equipment
  • Broadcast equipment
  • Military equipment
  • Medical equipment
  • Test and measurement equipment

Device Family Support

  • Agilex™ 7 devices (F-Tile)
  • Agilex™ 9 devices (F-Tile)

Design Tools

  • Platform Designer parameter editor in the Quartus® Prime software for design creation and compilation
  • Timing Analyzer in the Quartus® Prime software for timing analysis

  • ModelSim* - Intel® FPGA Starter Edition, Questa* Intel® FPGA Starter Edition, Riviera-PRO* , and, VCS* / VCS* MX simulator software for design simulation