F-Tile JESD204B Intel® FPGA IP User Guide

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ID 723907
Date 4/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. F-Tile JESD204B IP Quick Reference 2. About the F-Tile JESD204B Intel® FPGA IP 3. Getting Started 4. F-Tile JESD204B IP Functional Description 5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines 6. F-Tile JESD204B IP Debug Guidelines 7. F-Tile JESD204B Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile JESD204B Intel® FPGA IP User Guide
2. About the F-Tile JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. F-Tile JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. F-Tile JESD204B IP Design Considerations 3.8. F-Tile JESD204B Intel® FPGA IP Parameters 3.9. F-Tile JESD204B IP Component Files
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the F-Tile JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.7. F-Tile JESD204B IP Design Considerations x
3.7.1. Integrating the F-Tile JESD204B IP in Platform Designer 3.7.2. Pin Assignments 3.7.3. Adding External System PLL
4. F-Tile JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. System PLL Clock
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Register Map and Definition 4.7.3. Transmitter Registers 4.7.4. Receiver Registers
5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. F-Tile JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. F-Tile JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment
1. F-Tile JESD204B IP Quick Reference
2. About the F-Tile JESD204B Intel® FPGA IP
3. Getting Started
4. F-Tile JESD204B IP Functional Description
5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines
6. F-Tile JESD204B IP Debug Guidelines
7. F-Tile JESD204B Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile JESD204B Intel® FPGA IP User Guide

4.5.3. FPGA–DAC Subsystem Reset Sequence

Figure 19. FPGA–DAC Subsystem Reset Sequence Timing Diagram

The recommended FPGA – DAC subsystem bring-up sequence:

  1. The User Logic asserts IP and configuration reset to the SIP TX, jesd204_tx_rst_n = 0, jesd204_tx_avs_rst_n= 0 and reconfig_xcvr_reset = 1. jesd204_tx_out_of_reset is an output status to inform USER the IP MAC’s current reset status. jesd204_tx_out_of_reset = 0 indicates the MAC is under reset.
    Note: If User asserts jesd204_tx_avs_rst_n/reconfig_xcvr_reset, jesd204_tx_rst_n is required to be asserted as well. User could opt to assert jesd204_tx_rst_n without jesd204_tx_avs_rst_n/reconfig_xcvr_reset.
  2. Wait for Core PLL to lock. After which the User Logic deassert jesd204_tx_avs_rst_n/reconfig_xcvr_reset and perform configurations of the tile and Soft IP.
  3. After all relevant tile channels are fully in RESET, the IP asserts jesd204_tx_rst_ack_n to the USER LOGIC. Knowing the relevant channels are in proper reset states, the USER LOGIC can release the reset to the IP’s tile when it is ready to do so (jesd204_tx_rst_n = 1). User could use jesd204_tx_rst_ack_n for this purpose (to know when to deassert jesd204_tx_rst_n =1)
  4. The User Logic deassert the reset, jesd204_tx_rst_n = 1.
  5. Asserts jesd204_tx_out_of_reset = 1 to user. You must synchronize jesd204_tx_out_of_reset to rxlink_clk or rxframe_clk domain before use. TX SIP is operational.
  6. For Subclass 1, if the continuous SYSREF pulses from the clock generator are present when the TX link reset is deasserted, the TX link initializes. If the SYSREF pulse is not present, trigger the clock generator to provide a SYSREF pulse to initialize the link after jesd204_tx_out_of_reset = 1.
  7. When IP is ready to receive data from application, assert jesd204_tx_frame_ready = 1 and jesd204_tx_link_ready = 1.
  8. Anytime user requires a reset to MAC+PHY, wait for jesd204_tx_rst_ack_n=1. Assertion of jesd204_tx_rst_n=0 resets all logics in the IP.
  9. The IP asserts jesd204_tx_rst_ack_n=0 and jesd204_tx_out_of_reset = 0 to indicate to USER that reset sequence is completed.
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