1

Input

Transceiver reference clock signal.

1

Input

RX link clock signal used by the Avalon® streaming interface. This clock is equal to RX data rate divided by 40.

For Subclass 1, you cannot use the output of rxphy_clk signal as rxlink_clk signal. To sample SYSREF correctly, the core PLL must provide the rxlink_clk signal and must be configured as normal operating mode.

1

Input

From User. Async Assertion and Deassertion.

Assertion triggers reset sequence to MAC and PHY(Tile). Reset sequence completion indicated by assertion rx_rst_ack_n.

Deassertion triggers out-of-reset sequence. Out of reset completion indicates by deassertion of rx_rst_ack_n.

User is required to assert this reset if rx_avs_rst_n is asserted.

1

Output

1

Output

To indicate the reset status of the SIP link layer. Async Assertion and Deassertion. (IP uses avs_clk or reconfig_xcvr_clk internally). User may optionally observe jesd204_rx_out_of_reset = 1 to indicate SIP out of reset to pulse SYSREF for subclass 1. User must synchronize this signal before use.

0: SIP in reset

1: SIP out of reset

L

Output

Transceiver recovered clock signal. This clock is derived from the clock data recovery (CDR) and the frequency depends on the F-Tile JESD204B IP core data rate.

• For PCS option in Hard PCS or Soft PCS mode, this clock has the same frequency as the rxlink_clk signal.
• For PCS option in PMA Direct mode, this clock is half the frequency of rxlink_clk signal.

L

Input

Differential high-speed serial input data. The clock is recovered from the serial data stream.

L

Input

Differential high-speed serial input data. The clock is recovered from the serial data stream.

1

Input

Signal is synchronous with reconfig_xcvr_clk.

Only available when Transceiver Dynamic Reconfiguration option is enabled.

1

Input

Signal is synchronous with reconfig_xcvr_clk.

Only available when Transceiver Dynamic Reconfiguration option is enabled.

log2(L)+17:0

Input

Signal is synchronous with reconfig_xcvr_clk.

Each XCVR lanes address=18bits. Upper Ceiling(log2(L)) bits are lane select.

Only available when Transceiver Dynamic Reconfiguration option is enabled.

Input

Signal is synchronous with reconfig_xcvr_clk.

Only available when Transceiver Dynamic Reconfiguration option is enabled.

Output

Signal is synchronous with reconfig_xcvr_clk.

Only available when Transceiver Dynamic Reconfiguration option is enabled.

1

Output

Signal is synchronous with reconfig_xcvr_clk.

Only available when Transceiver Dynamic Reconfiguration option is enabled.

Input

Byte Enable. If byteenable[3:0] is 4’b1111, uses 32-bit Dword Access; otherwise uses byte access.

Only available when Transceiver Dynamic Reconfiguration option is enabled.

L*32

Output

Signal is synchronous with rxlink_clk.

Indicates a 32-bit data from the DLL to the transport layer. The data format is big endian, where the earliest octet is placed in bit [31:24] and the latest octet is placed in bit [7:0].

1

Output

Signal is synchronous with rxlink_clk.

Indicates whether the data to the transport layer is valid or invalid. The Avalon® streaming source interface in the RX core cannot be backpressured and transmits the data when the jesd204_rx_data_valid signal is asserted.

• 0—data is invalid
• 1—data is valid

1

Input

Signal is synchronous with rxlink_clk.

Indicates that the Avalon® streaming sink interface in the transport layer is ready to receive data.

1

Input

Signal is synchronous with rxlink_clk.

Indicates an empty data stream due to invalid data. This signal is asserted high to indicate an error during data transfer from the RX core to the transport layer.

1

Input

The Avalon® memory-mapped interface clock signal. This clock is asynchronous to all the functional clocks in the F-Tile JESD204B IP core. The F-Tile JESD204B IP core can handle any cross clock ratio and therefore the clock frequency can range from 75 MHz to 125 MHz.

1

Input

This reset is associated with the jesd204_rx_avs_clk signal. This reset is an active low signal. You can assert this reset signal asynchronously but must deassert it synchronously to the jesd204_rx_avs_clk signal. After you deassert this signal, the CPU can configure the CSRs.

1

Input

Signal is synchronous with rx_avs_clk.

When this signal is present, the slave port ignores all Avalon® memory-mapped signals unless this signal is asserted. This signal must be used in combination with read or write. If the Avalon® memory-mapped bus does not support chip select, you are recommended to tie this port to 1.

8

Input

Signal is synchronous with rx_avs_clk.

For Avalon® memory-mapped slave, the interconnect translates the byte address into a word address in the address space so that each slave access is for a word of data. For example, address = 0 selects the first word of the slave and address = 1 selects the second word of the slave.

32

Input

Signal is synchronous with rx_avs_clk.

32-bit data for write transfers. The width of this signal and the jesd204_rx_avs_readdata[31:0] signal must be the same if both signals are present.

1

Input

Signal is synchronous with rx_avs_clk.

This signal is asserted to indicate a read transfer. This is an active high signal and requires the jesd204_rx_avs_readdata[31:0] signal to be in use.

1

Input

Signal is synchronous with rx_avs_clk.

This signal is asserted to indicate a write transfer. This is an active high signal and requires the jesd204_rx_avs_writedata[31:0] signal to be in use.

32

Output

Signal is synchronous with rx_avs_clk.

32-bit data driven from the Avalon® memory-mapped slave to master in response to a read transfer.

1

Output

Signal is synchronous with rx_avs_clk.

This signal is asserted by the Avalon® memory-mapped slave to indicate that it is unable to respond to a read or write request. The F-Tile JESD204B IP core ties this signal to 0 to return the data in the access cycle.

1

Input

SYSREF signal for JESD204B Subclass 1 implementation.

For Subclass 0 and Subclass 2 mode, tie-off this signal to 0.

1

Output

Indicates a SYNC~ from the receiver. This is an active low signal and is asserted 0 to indicate a synchronization request. Instead of reporting the link error through this signal, the F-Tile JESD204B IP core uses the jesd204_rx_int signal to interrupt the CPU.

For multilink synchronization, you can optionally connect the DEV_SYNC_N from each IP core to the input of an AND gate. The output of the AND gate is exported to the FPGA pins for connection to the analog-to-digital converters. Refer to AN803 and AN804 for more information about the connection guidelines.

4

Output

Indicates a start of frame.

• [3]—start of frame for jesd204_rx_link_data[31:24]
• [2]—start of frame for jesd204_rx_link_data[23:16]
• [1]—start of frame for jesd204_rx_link_data[15:8]
• [0]—start of frame for jesd204_rx_link_data[7:0]

4

Output

Indicates a start of multiframe.

• [3]—start of multiframe for jesd204_rx_link_data[31:24]
• [2]—start of multiframe for jesd204_rx_link_data[23:16]
• [1]—start of multiframe for jesd204_rx_link_data[15:8]
• [0]—start of multiframe for jesd204_rx_link_data[7:0]

1

Output

Indicates that all lanes for this device are aligned.

1

Input

Aligns all lanes for this device.

For multidevice synchronization, input all the dev_lane_aligned signals to an AND gate and connect the AND gate output to this pin.

For single device support, connect the dev_lane_aligned signal back to this signal.

5

Output

Indicates the number of active lanes for the link. The transport layer can use this signal as a run-time parameter.

8

Output

Indicates the number of octets per frame. The transport layer can use this signal as a run-time parameter.

5

Output

Indicates the number of frames per multiframe. The transport layer can use this signal as a run-time parameter.

8

Output

Indicates the number of converters for the link. The transport layer can use this signal as a run-time parameter.

2

Output

Indicates the number of control bits per sample. The transport layer can use this signal as a run-time parameter.

5

Output

Indicates the converter resolution. The transport layer can use this signal as a run-time parameter.

5

Output

Indicates the total number of bits per sample. The transport layer can use this signal as a run-time parameter.

5

Output

Indicates the number of samples per converter per frame cycle. The transport layer can use this signal as a run-time parameter.

1

Output

Indicates the high density data format. The transport layer can use this signal as a run-time parameter.

5

Output

Indicates the number of control words per frame clock period per link. The transport layer can use this signal as a run-time parameter.

L

Output

Indicates which lane is powered down. You need to set this signal if you have configured the link and want to reduce the number of active lanes.

1

Output

Interrupt pin for the F-Tile JESD204B IP core. Interrupt is asserted when any error is detected. Configure the rx_err_enable register to set the type of error that can trigger an interrupt.

L*32

Input

Signal is synchronous with rxlink_clk.

Optional signal for parallel data to the DLL in TX to RX loopback testing. ¹¹

4

Output

Indicates the test mode for the F-Tile JESD204B IP core and the test pattern for the test pattern checker in the design example.

Refer to the rx_test register in the register map.

L

Input

Signal is synchronous with rxlink_clk.

Optional signal to indicate valid data for each byte in TX to RX loopback testing. ¹¹

L*4

Input

Optional signal to indicate the K character value for each byte in TX to RX loopback testing. ¹¹

L*4

Input

Signal is synchronous with rxlink_clk.

Optional signal to indicate 8B/10B error. ¹¹

L*4

Input

Signal is synchronous with rxlink_clk.

Optional signal to indicate running disparity. ¹¹